PCI: tegra: Fix extended configuration space mapping

The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space.  This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 42241b5bdf0250ceca88b1aaed6b9e387d705640..6329be3d4695ed3aa29783735f915a2cce7a4e0f 100644 (file)
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -383,7 +383,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
        for (i = 0; i < 16; i++) {
                unsigned long virt = (unsigned long)bus->area->addr +
                                     i * SZ_64K;
-               phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;
+               phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
 
                err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
                if (err < 0) {