arm64: dts: r8a7795: Add CA53 L2 cache-controller node

Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index ea56066c2260bc3813b8482b2a34cfe52e590a55..e32b652c8fd015b7ddc631a10a71ae387cfbd7a7 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -72,6 +72,12 @@
                cache-level = <2>;
        };
 
+       L2_CA53: cache-controller@1 {
+               compatible = "cache";
+               cache-unified;
+               cache-level = <2>;
+       };
+
        extal_clk: extal {
                compatible = "fixed-clock";
                #clock-cells = <0>;