microblaze: Add PVR for endians plus detection

Upcomming microblaze version will support little-endian.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Acked-by: Grant Likely <grant.likely@secretlab.ca>

diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
index b4f5ca33aebf09a831226022ae0b9513c8344322..0d4f0ce3ff7c6a5d4846ac8135f17a6499f95c6f 100644 (file)
--- a/arch/microblaze/include/asm/cpuinfo.h
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -38,6 +38,7 @@ struct cpuinfo {
        u32 use_exc;
        u32 ver_code;
        u32 mmu;
+       u32 endian;
 
        /* CPU caches */
        u32 use_icache;

diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 316105531d552cfd0c94441b4b855488914f9ce5..37db96a15b4544fdf7c08e869d440a698340a6ad 100644 (file)
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -32,6 +32,7 @@ struct pvr_s {
 #define PVR0_USE_DCACHE_MASK           0x01000000
 #define PVR0_USE_MMU                   0x00800000
 #define PVR0_USE_BTC                   0x00400000
+#define PVR0_ENDI                      0x00200000
 #define PVR0_VERSION_MASK              0x0000FF00
 #define PVR0_USER1_MASK                        0x000000FF
 
@@ -209,6 +210,8 @@ struct pvr_s {
 #define PVR_MMU_TLB_ACCESS(pvr)        (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
 #define PVR_MMU_ZONES(pvr)     (pvr.pvr[11] & PVR11_MMU_ZONES)
 
+/* endian */
+#define PVR_ENDIAN(pvr)        (pvr.pvr[0] & PVR0_ENDI)
 
 int cpu_has_pvr(void);
 void get_pvr(struct pvr_s *pvr);

diff --git a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
index f72dbd66c84411041c59705f72d253ee896af574..f70a6047f08e3e581b32dd65866ad4ebf45e5423 100644 (file)
--- a/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-pvr-full.c
@@ -72,6 +72,7 @@ void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu)
        CI(pvr_user2, USER2);
 
        CI(mmu, USE_MMU);
+       CI(endian, ENDIAN);
 
        CI(use_icache, USE_ICACHE);
        CI(icache_tagbits, ICACHE_ADDR_TAG_BITS);

diff --git a/arch/microblaze/kernel/cpu/cpuinfo-static.c b/arch/microblaze/kernel/cpu/cpuinfo-static.c
index 6095aa6b5c88ef17d6cdab7d7393d49dfd0ee286..b16b994ca3d25b81165b1d95492e0c550cc9d14e 100644 (file)
--- a/arch/microblaze/kernel/cpu/cpuinfo-static.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo-static.c
@@ -119,6 +119,7 @@ void __init set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu)
        ci->pvr_user2 = fcpu(cpu, "xlnx,pvr-user2");
 
        ci->mmu = fcpu(cpu, "xlnx,use-mmu");
+       ci->endian = fcpu(cpu, "xlnx,endianness");
 
        ci->ver_code = 0;
        ci->fpga_family_code = 0;

diff --git a/arch/microblaze/kernel/cpu/mb.c b/arch/microblaze/kernel/cpu/mb.c
index 7086e356428163bc77d9ddaee75b2f7565249a12..b4048af026158e79c1422b0553d540d30f53da13 100644 (file)
--- a/arch/microblaze/kernel/cpu/mb.c
+++ b/arch/microblaze/kernel/cpu/mb.c
@@ -51,11 +51,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        count = seq_printf(m,
                        "CPU-Family:    MicroBlaze\n"
                        "FPGA-Arch:     %s\n"
-                       "CPU-Ver:       %s\n"
+                       "CPU-Ver:       %s, %s endian\n"
                        "CPU-MHz:       %d.%02d\n"
                        "BogoMips:      %lu.%02lu\n",
                        fpga_family,
                        cpu_ver,
+                       cpuinfo.endian ? "little" : "big",
                        cpuinfo.cpu_clock_freq /
                        1000000,
                        cpuinfo.cpu_clock_freq %

diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts
index ef667d125ce02be9fe695b7a0418b725c67814d4..3f85df2b73b3ecd21fb4a0d4d118544e4fc290f0 100644 (file)
--- a/arch/microblaze/platform/generic/system.dts
+++ b/arch/microblaze/platform/generic/system.dts
@@ -85,6 +85,7 @@
                        xlnx,dynamic-bus-sizing = <0x1>;
                        xlnx,edge-is-positive = <0x1>;
                        xlnx,family = "virtex5";
+                       xlnx,endianness = <0x1>;
                        xlnx,fpu-exception = <0x1>;
                        xlnx,fsl-data-size = <0x20>;
                        xlnx,fsl-exception = <0x0>;