drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/

MI_STORE_DWORD_IMM length has been the same ever since gen4. Rename
the define to avoid potential confusion if someone tries to use this
on pre-gen8.

Also correct the comment on MI_MEM_VIRTUAL bit. It's present on 945,g33
and 965 only.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add USE_GGTT define for g4x+ too.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc03facd587a6f96e7b8fb3b21d6fbf03ed86fa6..82da2323896c122ddd1c447ebdb091d9215c3004 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -293,8 +293,9 @@
 #define   MI_SEMAPHORE_POLL            (1<<15)
 #define   MI_SEMAPHORE_SAD_GTE_SDD     (1<<12)
 #define MI_STORE_DWORD_IMM     MI_INSTR(0x20, 1)
-#define MI_STORE_DWORD_IMM_GEN8        MI_INSTR(0x20, 2)
-#define   MI_MEM_VIRTUAL       (1 << 22) /* 965+ only */
+#define MI_STORE_DWORD_IMM_GEN4        MI_INSTR(0x20, 2)
+#define   MI_MEM_VIRTUAL       (1 << 22) /* 945,g33,965 */
+#define   MI_USE_GGTT          (1 << 22) /* g4x+ */
 #define MI_STORE_DWORD_INDEX   MI_INSTR(0x21, 1)
 #define   MI_STORE_DWORD_INDEX_SHIFT 2
 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 52e9952206d9dae1811c1e5126e2e4a4276c0d8c..7986eb3e50273735ffaf00c6e09073489a62de0c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1319,7 +1319,7 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
        if (ret)
                return ret;
 
-       cmd = MI_STORE_DWORD_IMM_GEN8;
+       cmd = MI_STORE_DWORD_IMM_GEN4;
        cmd |= MI_GLOBAL_GTT;
 
        intel_logical_ring_emit(ringbuf, cmd);