}
EXPORT_SYMBOL(ipu_init_sync_panel);
+void ipu_uninit_sync_panel(int disp)
+{
+ unsigned long lock_flags;
+ uint32_t reg;
+ uint32_t di_gen;
+
+ spin_lock_irqsave(&ipu_lock, lock_flags);
+
+ di_gen = __raw_readl(DI_GENERAL(disp));
+ di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
+ __raw_writel(di_gen, DI_GENERAL(disp));
+
+ reg = __raw_readl(DI_POL(disp));
+ reg |= 0x3ffffff;
+ __raw_writel(reg, DI_POL(disp));
+
+ spin_unlock_irqrestore(&ipu_lock, lock_flags);
+}
+EXPORT_SYMBOL(ipu_uninit_sync_panel);
int ipu_init_async_panel(int disp, int type, uint32_t cycle_time,
uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
ipu_disable_channel(mxc_fbi->ipu_ch, true);
+ ipu_uninit_sync_panel(mxc_fbi->ipu_di);
ipu_uninit_channel(mxc_fbi->ipu_ch);
break;
case FB_BLANK_UNBLANK:
uint16_t v_sync_width, uint16_t v_end_width,
uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+void ipu_uninit_sync_panel(int disp);
+
int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos,
int16_t y_pos);
int32_t ipu_disp_get_window_pos(ipu_channel_t channel, int16_t *x_pos,