drm/i915: Add wa_ctx_emit_reg()

Add a helper for emitting register offsets (for LRI/SRM) into the w/a
batch buffer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-21-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c12db1aa20b0fe8221faffb622355c6c1446832d..1845eab42d222fced621c4772f4a32f883a64c3c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1118,6 +1118,8 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
                batch[__index] = (cmd);                                 \
        } while (0)
 
+#define wa_ctx_emit_reg(batch, index, reg) \
+       wa_ctx_emit((batch), (index), (reg))
 
 /*
  * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
@@ -1152,12 +1154,12 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
 
        wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
                                   MI_SRM_LRM_GLOBAL_GTT));
-       wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+       wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
        wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
        wa_ctx_emit(batch, index, 0);
 
        wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-       wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+       wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
        wa_ctx_emit(batch, index, l3sqc4_flush);
 
        wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
@@ -1170,7 +1172,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring,
 
        wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
                                   MI_SRM_LRM_GLOBAL_GTT));
-       wa_ctx_emit(batch, index, GEN8_L3SQCREG4);
+       wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
        wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256);
        wa_ctx_emit(batch, index, 0);
 
@@ -1341,7 +1343,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
        if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
            IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
-               wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
+               wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
                wa_ctx_emit(batch, index,
                            _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
                wa_ctx_emit(batch, index, MI_NOOP);