OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz

This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze.  The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.

Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 9c2d0465a83c4901b86d0c18e16b65ef564580b5..e6b112590d7d0b65091342dcb1ef5c2492db31a7 100644 (file)
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -143,7 +143,7 @@ return_to_sdram:
 unlock_dll:
        ldr     r11, omap3_sdrc_dlla_ctrl
        ldr     r12, [r11]
-       and     r12, r12, #FIXEDDELAY_MASK
+       bic     r12, r12, #FIXEDDELAY_MASK
        orr     r12, r12, #FIXEDDELAY_DEFAULT
        orr     r12, r12, #DLLIDLE_MASK
        str     r12, [r11]              @ (no OCP barrier needed)