add r1, r1, #LOCK_DELAY
wait_until r1, r7, r3
- adr r5, tegra30_sdram_pad_save
+ adr r5, tegra_sdram_pad_save
ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
+tegra30_sdram_pad_address_end:
tegra114_sdram_pad_address:
.word TEGRA_EMC0_BASE + EMC_CFG @0x0
.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
+tegra114_sdram_pad_adress_end:
tegra30_sdram_pad_size:
- .word tegra114_sdram_pad_address - tegra30_sdram_pad_address
+ .word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
tegra114_sdram_pad_size:
- .word tegra30_sdram_pad_size - tegra114_sdram_pad_address
+ .word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
- .type tegra30_sdram_pad_save, %object
-tegra30_sdram_pad_save:
- .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
+ .type tegra_sdram_pad_save, %object
+tegra_sdram_pad_save:
+ .rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
.long 0
.endr
*/
tegra30_sdram_self_refresh:
- adr r8, tegra30_sdram_pad_save
+ adr r8, tegra_sdram_pad_save
tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
cmp r10, #TEGRA30
adreq r2, tegra30_sdram_pad_address