clk: tegra: Fix pll_a1 iddq register, add pll_a1

pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add
pll_a1 to the set of clocks defined for Tegra210.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 2896d2e783cecc363ec4966bdd8bb408bc9faee4..2ef8d49537c2094ce87167ed9994934bc590b1c0 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -1772,7 +1772,7 @@ static struct tegra_clk_pll_params pll_a1_params = {
        .misc_reg = PLLA1_MISC0,
        .lock_mask = PLLCX_BASE_LOCK,
        .lock_delay = 300,
-       .iddq_reg = PLLA1_MISC0,
+       .iddq_reg = PLLA1_MISC1,
        .iddq_bit_idx = PLLCX_IDDQ_BIT,
        .reset_reg = PLLA1_MISC0,
        .reset_bit_idx = PLLCX_RESET_BIT,
@@ -2209,6 +2209,7 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
        [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
        [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
        [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
+       [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
 };
 
 static struct tegra_devclk devclks[] __initdata = {