]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
drm/i915: Set primary_disabled in intel_{enable, disable}_plane
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 1 Oct 2013 15:02:10 +0000 (18:02 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Oct 2013 10:46:58 +0000 (12:46 +0200)
If the primary gets marked as disabled while the pipe is off for
instance, we should still re-enable it when the pipe is turned on,
unless the sprite covers it fully also in that configuration.
Unfortunately we do the plane visibility checks only in the sprite code,
which is executed after the primary enabling when turning the pipe off.

Ideally we should compute the plane visibility before touching the
hardware at all, but for now just set the primary_disabld flag
in intel_{enable,disable}_plane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c

index a003bc572a00d07234218438f50c0d1a55f40918..579becbc46ecd9df3f013178101c45db03f217cd 100644 (file)
@@ -1832,12 +1832,16 @@ void intel_flush_display_plane(struct drm_i915_private *dev_priv,
 static void intel_enable_plane(struct drm_i915_private *dev_priv,
                               enum plane plane, enum pipe pipe)
 {
+       struct intel_crtc *intel_crtc =
+               to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
        int reg;
        u32 val;
 
        /* If the pipe isn't enabled, we can't pump pixels and may hang */
        assert_pipe_enabled(dev_priv, pipe);
 
+       intel_crtc->primary_disabled = false;
+
        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if (val & DISPLAY_PLANE_ENABLE)
@@ -1859,9 +1863,13 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
 static void intel_disable_plane(struct drm_i915_private *dev_priv,
                                enum plane plane, enum pipe pipe)
 {
+       struct intel_crtc *intel_crtc =
+               to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
        int reg;
        u32 val;
 
+       intel_crtc->primary_disabled = true;
+
        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if ((val & DISPLAY_PLANE_ENABLE) == 0)