PCI: designware: Fix comment for setting number of lanes

Corrects comment for setting number of lanes.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
(cherry picked from commit 66c5c34bf80c28d370eb9bcf30153ea0304a288a)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6eca144752ef782fa757092c6d4516cf2da31383..a9a62ce4bf05cac4fa6a3ba27c0b38971ca75863 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
        u32 membase;
        u32 memlimit;
 
-       /* set the number of lines as 4 */
+       /* set the number of lanes */
        dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
        val &= ~PORT_LINK_MODE_MASK;
        switch (pp->lanes) {