The base address of exception vectors.
config ARM_PATCH_PHYS_VIRT
- - - -- bool "Patch physical to virtual translations at runtime"
- -- bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
- -- depends on EXPERIMENTAL
++++++ ++ bool "Patch physical to virtual translations at runtime" if EMBEDDED
++++++ ++ default y
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
kernel in system memory.
This can only be used with non-XIP MMU kernels where the base
------ -- of physical memory is at a 16MB boundary, or theoretically 64K
------ -- for the MSM machine class.
++++++ ++ of physical memory is at a 16MB boundary.
++++++ ++
++++++ ++ Only disable this option if you know that you do not require
++++++ ++ this feature (eg, building a kernel for a single machine) and
++++++ ++ you need to shrink the kernel to the minimal size.
+ +
-- --- -config ARM_PATCH_PHYS_VIRT_16BIT
- def_bool y
- depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
- help
- This option extends the physical to virtual translation patching
- to allow physical memory down to a theoretical minimum of 64K
- boundaries.
++ ++ +
- - config ARM_PATCH_PHYS_VIRT_16BIT
+++++ +++config GENERIC_BUG
+ def_bool y
----- -- depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
----- -- help
----- -- This option extends the physical to virtual translation patching
----- -- to allow physical memory down to a theoretical minimum of 64K
----- -- boundaries.
+++++ +++ depends on BUG
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
+ ++ ++ config ARM_ERRATA_364296
+ ++ ++ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
+ ++ ++ depends on CPU_V6 && !SMP
+ ++ ++ help
+ ++ ++ This options enables the workaround for the 364296 ARM1136
+ ++ ++ r0p2 erratum (possible cache data corruption with
+ ++ ++ hit-under-miss enabled). It sets the undocumented bit 31 in
+ ++ ++ the auxiliary control register and the FI bit in the control
+ ++ ++ register, thus disabling hit-under-miss without putting the
+ ++ ++ processor into full low interrupt latency mode. ARM11MPCore
+ ++ ++ is not affected.
+ ++ ++
++ ++++++config ARM_ERRATA_764369
++ ++++++ bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
++ ++++++ depends on CPU_V7 && SMP
++ ++++++ help
++ ++++++ This option enables the workaround for erratum 764369
++ ++++++ affecting Cortex-A9 MPCore with two or more processors (all
++ ++++++ current revisions). Under certain timing circumstances, a data
++ ++++++ cache line maintenance operation by MVA targeting an Inner
++ ++++++ Shareable memory region may fail to proceed up to either the
++ ++++++ Point of Coherency or to the Point of Unification of the
++ ++++++ system. This workaround adds a DSB instruction before the
++ ++++++ relevant cache maintenance functions and sets a specific bit
++ ++++++ in the diagnostic control register of the SCU.
++ ++++++
endmenu
source "arch/arm/common/Kconfig"