ASoC: wm_adsp: Set ADSP1 clock rate to match sys clock

Sets the ADSP1 clock rate to match the system clock
rate. To support this the codec driver provides
details of register containing the system clock
control bits.

Signed-off-by: Chris Rattray <crattray@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

diff --git a/sound/soc/codecs/wm_adsp.c b/sound/soc/codecs/wm_adsp.c
index 5841285c213fd3288362ed76f9284842b0a05493..9e311622190ef8730ea12a60e20be6d2a864bdf5 100644 (file)
--- a/sound/soc/codecs/wm_adsp.c
+++ b/sound/soc/codecs/wm_adsp.c
@@ -103,6 +103,13 @@
 #define ADSP1_START_SHIFT                      0  /* DSP1_START */
 #define ADSP1_START_WIDTH                      1  /* DSP1_START */
 
+/*
+ * ADSP1 Control 31
+ */
+#define ADSP1_CLK_SEL_MASK                0x0007  /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_SHIFT                    0  /* CLK_SEL_ENA */
+#define ADSP1_CLK_SEL_WIDTH                    3  /* CLK_SEL_ENA */
+
 #define ADSP2_CONTROL  0
 #define ADSP2_CLOCKING 1
 #define ADSP2_STATUS1  4
@@ -806,12 +813,38 @@ int wm_adsp1_event(struct snd_soc_dapm_widget *w,
        struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
        struct wm_adsp *dsp = &dsps[w->shift];
        int ret;
+       int val;
 
        switch (event) {
        case SND_SOC_DAPM_POST_PMU:
                regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
                                   ADSP1_SYS_ENA, ADSP1_SYS_ENA);
 
+               /*
+                * For simplicity set the DSP clock rate to be the
+                * SYSCLK rate rather than making it configurable.
+                */
+               if(dsp->sysclk_reg) {
+                       ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
+                       if (ret != 0) {
+                               adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
+                               ret);
+                               return ret;
+                       }
+
+                       val = (val & dsp->sysclk_mask)
+                               >> dsp->sysclk_shift;
+
+                       ret = regmap_update_bits(dsp->regmap,
+                                                dsp->base + ADSP1_CONTROL_31,
+                                                ADSP1_CLK_SEL_MASK, val);
+                       if (ret != 0) {
+                               adsp_err(dsp, "Failed to set clock rate: %d\n",
+                                        ret);
+                               return ret;
+                       }
+               }
+
                ret = wm_adsp_load(dsp);
                if (ret != 0)
                        goto err;

diff --git a/sound/soc/codecs/wm_adsp.h b/sound/soc/codecs/wm_adsp.h
index 41206d79e038c5c65441704794fab8665a98cff4..cb8871a3ec0015854c6d13bebb1055661b7cf4be 100644 (file)
--- a/sound/soc/codecs/wm_adsp.h
+++ b/sound/soc/codecs/wm_adsp.h
@@ -40,6 +40,9 @@ struct wm_adsp {
        struct regmap *regmap;
 
        int base;
+       int sysclk_reg;
+       int sysclk_mask;
+       int sysclk_shift;
 
        struct list_head alg_regions;