#define bf_frmlen bf_state.bfs_frmlen
#define bf_retries bf_state.bfs_retries
#define bf_keyix bf_state.bfs_keyix
-#define bf_keytype bf_state.bfs_keytype
#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
u8 bfs_paprd;
unsigned long bfs_paprd_timestamp;
u32 bfs_keyix;
- enum ath9k_key_type bfs_keytype;
enum ath9k_internal_frame_type bfs_ftype;
};
* TODO - this could be improved to be dependent on the rate.
* The hardware can keep up at lower rates, but not higher rates
*/
- if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
+ if (tx_info->control.hw_key)
ndelim += ATH_AGGR_ENCRYPTDELIM;
/*
bf->bf_flags = setup_tx_flags(skb);
- bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
- if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
+ if (tx_info->control.hw_key) {
bf->bf_frmlen += tx_info->control.hw_key->icv_len;
bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
} else {
struct ath_desc *ds;
struct ath_atx_tid *tid;
struct ath_hw *ah = sc->sc_ah;
+ enum ath9k_key_type keytype;
int frm_type;
__le16 fc;
u8 tidno;
ds = bf->bf_desc;
ath9k_hw_set_desc_link(ah, ds, 0);
+ keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
- bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
+ bf->bf_keyix, keytype, bf->bf_flags);
ath9k_hw_filltxdesc(ah, ds,
skb->len, /* segment length */