ENGR00291876 usb: phy-mxs: add delay before set phyctrl.clkgate

There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phypwd, otherwise, the wakeup
signal may can't wake up controller.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit a7a99b979db9d0bf7277533a3a39ba09755768f0)

diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index 6f0f37c224df9615cbda3395269fedfac5abd6f3..0423d5688beab89ff12e1b65baefc973461ed579 100644 (file)
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -343,10 +343,16 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend)
                 * connect. The low speed connection will have problem at
                 * very rare cases during usb suspend and resume process.
                 */
-               if (low_speed_connection & vbus_is_on)
-                       writel(0xfffbffff, x->io_priv + HW_USBPHY_PWD);
-               else
+               if (low_speed_connection & vbus_is_on) {
+                       /*
+                        * If value to be set as pwd value is not 0xffffffff,
+                        * several 32Khz cycles are needed.
+                        */
+                       mxs_phy_clock_switch();
+                       writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
+               } else {
                        writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
+               }
                writel(BM_USBPHY_CTRL_CLKGATE,
                       x->io_priv + HW_USBPHY_CTRL_SET);
                clk_disable_unprepare(mxs_phy->clk);