drm/i915: Align DSPSURF to 128k on VLV/CHV

VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
docs got updated at some point to say that we need to align them to
128k, just like we do on gen4.

So far I've seen the problem manifest when the stride is an odd multiple
of 512 bytes, and the surface address meets the following pattern
'(addr & 0xf000) == 0x1000' (also == 0x2000 is problematic on VLV). The
result is a starcase effect (so some pages get dropped maybe?), with a
few pages here and there clearly getting scannout out at the wrong position.

I've not actually been able to reproduce this problem on gen4, so it's
not clear of the issue is any way related to the 128k restrictions
supposedly inherited from gen4. But let's hope the 128k alignment is
sufficient to hide it all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1d440e7e0344f1a47e72fbe1dc985fd19bfda2fe..e94a9a0a6d91ea49b3c630582ee0370b0f802a34 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2333,7 +2333,8 @@ static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
 {
        if (INTEL_INFO(dev_priv)->gen >= 9)
                return 256 * 1024;
-       else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv))
+       else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
+                IS_VALLEYVIEW(dev_priv))
                return 128 * 1024;
        else if (INTEL_INFO(dev_priv)->gen >= 4)
                return 4 * 1024;