Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel...

Daniel writes: (this pull is the one with the bad patch dropped)
First pile of fixes for 3.6 already, and I'm afraid it's a bit larger than
what I'd wish for. But I've moved all the feature-y stuff to -next, so
this really is all -fixes. Most of it is handling fallout from the hw
context stuff, discovered now that mesa git has started using them for
real. Otherwise all just small fixes:
- unbreak modeset=0 on gen6+ (regressed in next)
- const mismatch fix for ->mode_fixup
- simplify overly clever lvds modeset code (current code can totally
  confuse backlights, resulting in broken panels until a full power draw
  restores them).
- fix some fallout from the flushing_list disabling (regression only
  introduced in -next)
- DP link train improvements (this also kills the last 3.2 dp regression
  afaik)
- bugfix for the new ddc VGA detection on newer platforms
- minor backlight fixes (one of them a -next regression)
- only enable the required PM interrupts (to avoid waking up the cpu
  unnecessarily)
- some really minor bits (workaround clarification, make coverty happy,
  hsw init fix)
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: (23 commits)
  drm/i915: unbreak lastclose for failed driver init
  drm/i915: Set the context before setting up regs for the context.
  drm/i915: constify mode in crtc_mode_fixup
  drm/i915/lvds: ditch ->prepare special case
  drm/i915: dereferencing an error pointer
  drm/i915: fix invalid reference handling of the default ctx obj
  drm/i915: Add -EIO to the list of known errors for __wait_seqno
  drm/i915: Flush the context object from the CPU caches upon switching
  drm/i915: Make the lock for pageflips interruptible
  drm/i915: don't forget the PCH backlight registers
  drm/i915: Insert a flush between batches if the breadcrumb was dropped
  drm/i915: missing error case in init status page
  drm/i915: mask tiled bit when updating ILK sprites
  drm/i915: try to train DP even harder
  drm/i915: kill intel_ddc_probe
  drm/i915: check whether we actually received an edid in detect_ddc
  drm/i915: fix up PCH backlight #define mixup
  drm/i915: Add comments to explain the BSD tail write workaround
  drm/i915: Disable the BLT on pre-production SNB hardware
  drm/i915: initialize power wells in modeset_init_hw
  ...

diff --combined drivers/gpu/drm/i915/i915_irq.c
index 05014bc20ee8b9ec857c5775b87a74efc1091fc8,566f61b9e47c2ddd15d706d68ca4b4974e7fd197..8a3828528b9ddfa9678e7bfbf015bd7acdfdc29d
--- 1/drivers/gpu/drm/i915/i915_irq.c
--- 2/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@@ -495,6 -495,7 +495,6 @@@ static void gen6_queue_rps_work(struct 
         */
  
        spin_lock_irqsave(&dev_priv->rps_lock, flags);
 -      WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
        dev_priv->pm_iir |= pm_iir;
        I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
        POSTING_READ(GEN6_PMIMR);
@@@ -1066,6 -1067,7 +1066,7 @@@ static void i915_record_ring_state(stru
        struct drm_i915_private *dev_priv = dev->dev_private;
  
        if (INTEL_INFO(dev)->gen >= 6) {
+               error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
                error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
                error->semaphore_mboxes[ring->id][0]
                        = I915_READ(RING_SYNC_0(ring->mmio_base));

diff --combined drivers/gpu/drm/i915/intel_display.c
index bc25a24a08c50cb28964779b1bf46d2d5143648e,e9e476eca89f4b60e88b8ec8e3643b8cc0cb8817..f6159765f1ebe8cf8f6844c092deddd37bd44040
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -3573,7 -3573,7 +3573,7 @@@ void intel_encoder_destroy(struct drm_e
  }
  
  static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
-                                 struct drm_display_mode *mode,
+                                 const struct drm_display_mode *mode,
                                  struct drm_display_mode *adjusted_mode)
  {
        struct drm_device *dev = crtc->dev;
@@@ -6486,7 -6486,9 +6486,9 @@@ static int intel_crtc_page_flip(struct 
        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;
  
-       mutex_lock(&dev->struct_mutex);
+       ret = i915_mutex_lock_interruptible(dev);
+       if (ret)
+               goto cleanup;
  
        /* Reference the objects for the scheduled work. */
        drm_gem_object_reference(&work->old_fb_obj->base);
@@@ -6521,6 -6523,7 +6523,7 @@@ cleanup_pending
        drm_gem_object_unreference(&obj->base);
        mutex_unlock(&dev->struct_mutex);
  
+ cleanup:
        spin_lock_irqsave(&dev->event_lock, flags);
        intel_crtc->unpin_work = NULL;
        spin_unlock_irqrestore(&dev->event_lock, flags);
@@@ -7172,8 -7175,26 +7175,13 @@@ static void i915_disable_vga(struct drm
        POSTING_READ(vga_reg);
  }
  
 -static void ivb_pch_pwm_override(struct drm_device *dev)
 -{
 -      struct drm_i915_private *dev_priv = dev->dev_private;
 -
 -      /*
 -       * IVB has CPU eDP backlight regs too, set things up to let the
 -       * PCH regs control the backlight
 -       */
 -      I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
 -      I915_WRITE(BLC_PWM_CPU_CTL, 0);
 -      I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
 -}
 -
  void intel_modeset_init_hw(struct drm_device *dev)
  {
+       /* We attempt to init the necessary power wells early in the initialization
+        * time, so the subsystems that expect power to be enabled can work.
+        */
+       intel_init_power_wells(dev);
+ 
        intel_prepare_ddi(dev);
  
        intel_init_clock_gating(dev);
@@@ -7181,6 -7202,9 +7189,6 @@@
        mutex_lock(&dev->struct_mutex);
        intel_enable_gt_powersave(dev);
        mutex_unlock(&dev->struct_mutex);
 -
 -      if (IS_IVYBRIDGE(dev))
 -              ivb_pch_pwm_override(dev);
  }
  
  void intel_modeset_init(struct drm_device *dev)