#define BCSR6_UPC1_POS_EN 0x40
#define BCSR6_UPC1_ADDR_EN 0x20
#define BCSR6_UPC1_DEV2 0x10
-#define BCSR6_SD_ENABLE 0x04
+#define BCSR6_SD_CARD_1BIT 0x08
+#define BCSR6_SD_CARD_4BITS 0x04
#define BCSR6_TDM2G_EN 0x02
#define BCSR6_UCC7_RMII_EN 0x01
#define BCSR15_SMII6_DIS 0x08
#define BCSR15_SMII8_DIS 0x04
+#define BCSR15_QEUART_EN 0x01
#define BCSR16_UPC1_DEV2 0x02
+#define BCSR17_nUSBEN 0x80
+#define BCSR17_nUSBLOWSPD 0x40
+#define BCSR17_USBVCC 0x20
+#define BCSR17_USBMODE 0x10
#define BCSR17_FLASH_nWP 0x01
/*BCSR Utils functions*/
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
*/
#include <common.h>
+#include <hwconfig.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_esdhc.h>
#include "bcsr.h"
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
+ /* QE UART */
+ {0, 19, 1, 0, 2}, /* QEUART_TX */
+ {1, 17, 2, 0, 3}, /* QEUART_RX */
+ {0, 25, 1, 0, 1}, /* QEUART_RTS */
+ {1, 23, 2, 0, 1}, /* QEUART_CTS */
+
+ /* QE USB */
+ {5, 3, 1, 0, 1}, /* USB_OE */
+ {5, 4, 1, 0, 2}, /* USB_TP */
+ {5, 5, 1, 0, 2}, /* USB_TN */
+ {5, 6, 2, 0, 2}, /* USB_RP */
+ {5, 7, 2, 0, 1}, /* USB_RX */
+ {5, 8, 2, 0, 1}, /* USB_RN */
+ {2, 4, 2, 0, 2}, /* CLK5 */
+
+ /* SPI Flash, M25P40 */
+ {4, 27, 3, 0, 1}, /* SPI_MOSI */
+ {4, 28, 3, 0, 1}, /* SPI_MISO */
+ {4, 29, 3, 0, 1}, /* SPI_CLK */
+ {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
+
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}
+static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
+{
+ const char *status = "disabled";
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, alias);
+ if (off < 0) {
+ printf("WARNING: could not find %s alias: %s.\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+ if (err) {
+ printf("WARNING: could not set status for serial0: %s.\n",
+ fdt_strerror(err));
+ return;
+ }
+}
+
+/*
+ * Because of an erratum in prototype boards it is impossible to use eSDHC
+ * without disabling UART0 (which makes it quite easy to 'brick' the board
+ * by simply issung 'setenv hwconfig esdhc', and not able to interact with
+ * U-Boot anylonger).
+ *
+ * So, but default we assume that the board is a prototype, which is a most
+ * safe assumption. There is no way to determine board revision from a
+ * register, so we use hwconfig.
+ */
+
+static int prototype_board(void)
+{
+ if (hwconfig_subarg("board", "rev", NULL))
+ return hwconfig_subarg_cmp("board", "rev", "prototype");
+ return 1;
+}
+
+static int esdhc_disables_uart0(void)
+{
+ return prototype_board() ||
+ hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
+}
+
+static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ const char *devtype = "serial";
+ const char *compat = "ucc_uart";
+ const char *clk = "brg9";
+ u32 portnum = 0;
+ int off = -1;
+
+ if (!hwconfig("qe_uart"))
+ return;
+
+ if (hwconfig("esdhc") && esdhc_disables_uart0()) {
+ printf("QE UART: won't enable with esdhc.\n");
+ return;
+ }
+
+ fdt_board_disable_serial(blob, bd, "serial1");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
+ if (off < 0) {
+ printf("WARNING: unable to fixup device tree for "
+ "QE UART\n");
+ return;
+ }
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
+ continue;
+ break;
+ }
+
+ fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
+ fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
+ fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
+
+ setbits_8(&bcsr[15], BCSR15_QEUART_EN);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+int board_mmc_init(bd_t *bd)
+{
+ struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ u8 bcsr6 = BCSR6_SD_CARD_1BIT;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ printf("Enabling eSDHC...\n"
+ " For eSDHC to function, I2C2 ");
+ if (esdhc_disables_uart0()) {
+ printf("and UART0 should be disabled.\n");
+ printf(" Redirecting stderr, stdout and stdin to UART1...\n");
+ console_assign(stderr, "eserial1");
+ console_assign(stdout, "eserial1");
+ console_assign(stdin, "eserial1");
+ printf("Switched to UART1 (initial log has been printed to "
+ "UART0).\n");
+ bcsr6 |= BCSR6_SD_CARD_4BITS;
+ } else {
+ printf("should be disabled.\n");
+ }
+
+ /* Assign I2C2 signals to eSDHC. */
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
+ PLPPAR1_ESDHC_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
+ PLPDIR1_ESDHC_VAL);
+
+ /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
+ setbits_8(&bcsr[6], bcsr6);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+
+static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *status = "disabled";
+ int off = -1;
+
+ if (!hwconfig("esdhc"))
+ return;
+
+ if (esdhc_disables_uart0())
+ fdt_board_disable_serial(blob, bd, "serial0");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
+ if (off < 0)
+ break;
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx))
+ continue;
+
+ if (*idx == 1) {
+ fdt_setprop(blob, off, "status", status,
+ strlen(status) + 1);
+ break;
+ }
+ }
+}
+#else
+static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif
+
+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+
+ if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
+ clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+ else
+ setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+
+ if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
+ clrbits_8(&bcsr[17], BCSR17_USBVCC);
+ clrbits_8(&bcsr[17], BCSR17_USBMODE);
+ do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+ } else {
+ setbits_8(&bcsr[17], BCSR17_USBVCC);
+ setbits_8(&bcsr[17], BCSR17_USBMODE);
+ }
+
+ clrbits_8(&bcsr[17], BCSR17_nUSBEN);
+}
+
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
+ fdt_board_fixup_esdhc(blob, bd);
+ fdt_board_fixup_qe_uart(blob, bd);
+ fdt_board_fixup_qe_usb(blob, bd);
}
#endif
/* TLB 1 Initializations */
/*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
+ * TLBe 0: 64M Non-cacheable, guarded
* Out of reset this entry is only 4K.
+ * 0xfc000000 256K NAND FLASH (CS3)
+ * 0xfe000000 32M NOR FLASH (CS0)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
+ * TLBe 1: 256KB Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
+ 0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
{
sys_info_t sysinfo;
char buf[32];
- fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
strmhz(buf, sysinfo.freqDDRBus));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_400;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_533;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_667;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_800;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
/* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
- ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
- ddr_cfg_regs->cs[0].bnds = 0x0000001F;
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+ ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
}
else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
return ddr_size;
}
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
/*
* The workaround doesn't work on p2020 because the location
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE3: disabled\n");
}
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE1: disabled\n");
}
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pci1_hose, first_free_busno);
+ &pci1_hose, first_free_busno, 0);
} else {
printf (" PCI: disabled\n");
}
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, 0);
} else {
printf (" PCIE: disabled\n");
}
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
#ifdef CONFIG_PCIE1
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_PCIE2
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
+ 0, 5, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE3
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
+ 0, 6, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ 0, 7, BOOKE_PAGESZ_64M, 1),
#endif
};
*/
#include <common.h>
+#include <stdio_dev.h>
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
}
#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+
+#ifdef CONFIG_SERIAL_MULTI
+static void fdt_fill_multisername(char *sername, size_t maxlen)
+{
+ const char *outname = stdio_devices[stdout]->name;
+
+ if (strcmp(outname, "serial") > 0)
+ strncpy(sername, outname, maxlen);
+
+ /* eserial? */
+ if (strcmp(outname + 1, "serial") > 0)
+ strncpy(sername, outname + 1, maxlen);
+}
+#else
+static inline void fdt_fill_multisername(char *sername, size_t maxlen) {}
+#endif /* CONFIG_SERIAL_MULTI */
+
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
int err = 0;
char sername[9] = { 0 };
const char *path;
- sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
+ fdt_fill_multisername(sername, sizeof(sername) - 1);
+ if (!sername[0])
+ sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
err = node = fdt_path_offset(fdt, "/aliases");
if (node >= 0) {
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string
+
+# -mspe=yes is needed to have -mno-spe accepted by a buggy GCC;
+# see "[PATCH,rs6000] make -mno-spe work as expected" on
+# http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html
+PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes)
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
# Use default linker script. Board port can override in board/*/config.mk
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
- if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
+ if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
+ while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
+ ;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
+ }
#else
puts("disabled\n");
#endif
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
int off;
- ulong spin_tbl_addr = get_spin_addr();
+ ulong spin_tbl_addr = get_spin_phys_addr();
u32 bootpg = determine_mp_bootpg();
u32 id = get_my_id();
u32 *table, id = get_my_id();
if (nr == id) {
- table = (u32 *)get_spin_addr();
+ table = (u32 *)get_spin_virt_addr();
printf("table base @ 0x%p\n", table);
} else {
- table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
+ table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
printf("Running on cpu %d\n", id);
printf("\n");
printf("table @ 0x%p\n", table);
int cpu_release(int nr, int argc, char *argv[])
{
- u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
+ u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
if (nr == get_my_id()) {
return (gd->ram_size - 4096);
}
-ulong get_spin_addr(void)
+ulong get_spin_phys_addr(void)
{
extern ulong __secondary_start_page;
extern ulong __spin_table;
- ulong addr =
- (ulong)&__spin_table - (ulong)&__secondary_start_page;
- addr += 0xfffff000;
+ return (determine_mp_bootpg() +
+ (ulong)&__spin_table - (ulong)&__secondary_start_page);
+}
+
+ulong get_spin_virt_addr(void)
+{
+ extern ulong __secondary_start_page;
+ extern ulong __spin_table;
- return addr;
+ return (CONFIG_BPTR_VIRT_ADDR +
+ (ulong)&__spin_table - (ulong)&__secondary_start_page);
}
#ifdef CONFIG_FSL_CORENET
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_addr();
+ u32 *table = (u32 *)get_spin_virt_addr();
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
mtspr(SPRN_TBWU, 0);
mtspr(SPRN_TBWL, 0);
out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+
+#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
+ /*
+ * Disabling Boot Page Translation allows the memory region 0xfffff000
+ * to 0xffffffff to be used normally. Leaving Boot Page Translation
+ * enabled remaps 0xfffff000 to SDRAM which makes that memory region
+ * unusable for normal operation but it does allow OSes to easily
+ * reset a processor core to put it back into U-Boot's spinloop.
+ */
+ clrbits_be32(&ecm->bptr, 0x80000000);
+#endif
}
#else
static void plat_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_addr();
+ u32 *table = (u32 *)get_spin_virt_addr();
volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
out_be32(&gur->devdisr, devdisr);
+
+#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
+ /*
+ * Disabling Boot Page Translation allows the memory region 0xfffff000
+ * to 0xffffffff to be used normally. Leaving Boot Page Translation
+ * enabled remaps 0xfffff000 to SDRAM which makes that memory region
+ * unusable for normal operation but it does allow OSes to easily
+ * reset a processor core to put it back into U-Boot's spinloop.
+ */
+ clrbits_be32(&ecm->bptr, 0x80000000);
+#endif
}
#endif
void setup_mp(void)
{
extern ulong __secondary_start_page;
+ extern ulong __bootpg_addr;
ulong fixup = (ulong)&__secondary_start_page;
u32 bootpg = determine_mp_bootpg();
+ /* Store the bootpg's SDRAM address for use by secondary CPU cores */
+ __bootpg_addr = bootpg;
+
/* look for the tlb covering the reset page, there better be one */
- int i = find_tlb_idx((void *)0xfffff000, 1);
+ int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
/* we found a match */
if (i != -1) {
/* map reset page to bootpg so we can copy code there */
disable_tlb(i);
- set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
- 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
-
- memcpy((void *)0xfffff000, (void *)fixup, 4096);
- flush_cache(0xfffff000, 4096);
-
- disable_tlb(i);
-
- /* setup reset page back to 1:1, we'll use HW boot translation
- * to map this where we want
- */
- set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
+ set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+ memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
+
plat_mp_up(bootpg);
} else {
puts("WARNING: No reset page TLB. "
#include <asm/mp.h>
-ulong get_spin_addr(void);
+ulong get_spin_phys_addr(void);
+ulong get_spin_virt_addr(void);
u32 get_my_id(void);
#define BOOT_ENTRY_ADDR_UPPER 0
stw r3,ENTRY_R6_UPPER(r10)
stw r3,ENTRY_R6_LOWER(r10)
+ /* load r13 with the address of the 'bootpg' in SDRAM */
+ lis r13,toreset(__bootpg_addr)@h
+ ori r13,r13,toreset(__bootpg_addr)@l
+ lwz r13,0(r13)
+
/* setup mapping for AS = 1, and jump there */
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
- lis r11,(0xfffff000|MAS2_I)@h
- ori r11,r11,(0xfffff000|MAS2_I)@l
+ oris r11,r13,(MAS2_I)@h
+ ori r11,r13,(MAS2_I)@l
mtspr SPRN_MAS2,r11
- lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
- ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
+ oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
+ ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
mtspr SPRN_MAS3,r11
tlbwe
bl 1f
1: mflr r11
- addi r11,r11,28
+ /*
+ * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
+ * this mask to fixup the cpu spin table and the address that we want
+ * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
+ * bootpg is at 0x7ffff000 in SDRAM.
+ */
+ ori r13,r13,0xfff
+ and r11, r11, r13
+ and r10, r10, r13
+
+ addi r11,r11,(2f-1b)
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
mtspr SPRN_SRR1,r13
rfi
+ /*
+ * Allocate some space for the SDRAM address of the bootpg.
+ * This variable has to be in the boot page so that it can
+ * be accessed by secondary cores when they come out of reset.
+ */
+ .globl __bootpg_addr
+__bootpg_addr:
+ .long 0
+
.align L1_CACHE_SHIFT
.globl __spin_table
__spin_table:
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_MPC8569
+ gd->sdhc_clk = gd->bus_clk;
+#else
gd->sdhc_clk = gd->bus_clk / 2;
#endif
+#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno)
+ struct pci_controller *hose, int busno, int pcie_ep)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
+ if (pcie_ep) {
+ volatile pit_t *pi = &pci->pit[2];
+
+ pci_setup_indirect(hose, (u32)&pci->cfg_addr,
+ (u32)&pci->cfg_data);
+ out_be32(&pi->pitar, 0);
+ out_be32(&pi->piwbar, 0);
+ out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
+
+ fsl_pci_config_unlock(hose);
+ return 0;
+ }
+
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"brg-frequency", gd->brg_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
+ "clock-frequency", gd->qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
#endif
}
#define CONFIG_MAX_CPUS 1
#endif
+/*
+ * Provide a default boot page translation virtual address that lines up with
+ * Freescale's default e500 reset page.
+ */
+#if (defined(CONFIG_E500) && defined(CONFIG_MP))
+#ifndef CONFIG_BPTR_VIRT_ADDR
+#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
+#endif
+#endif
+
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
#define PIWAR_LOCAL 0x00f00000
#define PIWAR_READ_SNOOP 0x00050000
#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_IWS_4K 0x0000000b
u32 res2[3];
} pit_t;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno);
+ struct pci_controller *hose, int busno, int pcie_ep);
#define SET_STD_PCI_INFO(x, num) \
{ \
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
/* Serial Port */
#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define PLPPAR1_I2C_BIT_MASK 0x0000000F
#define PLPPAR1_I2C2_VAL 0x00000000
+#define PLPPAR1_ESDHC_VAL 0x0000000A
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
+#define PLPDIR1_ESDHC_VAL 0x00000006
/*
* General PCI
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
+
/*
* DDR config
*/
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
* 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
+ * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
@rm -f $(obj)tlb_table.c
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
#########################################################################
$(obj)%.o: $(obj)%.S
@rm -f $(obj)tlb_table.c
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+ @rm -f $(obj)nand_boot.c
+ ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
+endif
+
#########################################################################
$(obj)%.o: $(obj)%.S
void board_init_f(ulong bootflag)
{
- uint plat_ratio, bus_clk, sys_clk;
+ uint plat_ratio, bus_clk, sys_clk = 0;
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
uint val, temp, sysclk_mask;
projects / karo-tx-uboot.git / commitdiff