ARM: dts: imx6: phyFLEX: Add PCIe

Add PCIe support for Phytec phyFLEX-i.MX6 (PFL-A-02 and PBA-B-01).

Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 111b1f5021b9f3156a8734a38fa7b7a21daa9c8e..7634cc1c943613ea8ad1f5a116fd0bee4812d7ff 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -144,6 +144,10 @@
        status = "okay";
 };
 
+&pcie {
+       status = "okay";
+};
+
 &ssi2 {
        status = "okay";
 };

diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 8d718b55a07f55097de665232015e6fa5b118b33..2d721095a3696bb3d33a8294b2a2505313b7a333 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -283,6 +283,10 @@
                        >;
                };
 
+               pinctrl_pcie: pciegrp {
+                       fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
+               };
+
                pinctrl_uart3: uart3grp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
@@ -353,6 +357,13 @@
        };
 };
 
+&pcie {
+       pinctrl-name = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio4 17 0>;
+       status = "disabled";
+};
+
 &uart3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart3>;