},
};
-/* ripped from mite.h and mite_setup2() to avoid mite dependancy */
+/* ripped from mite.h and mite_setup2() to avoid mite dependency */
#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
#define WENAB (1 << 7) /* window enable */
*
* Mask Meaning
* ---------- ------------------------------------------
- * 0x00000001 Event 1 has occured
- * 0x00000010 Event 2 has occured
+ * 0x00000001 Event 1 has occurred
+ * 0x00000010 Event 2 has occurred
* 0x00000100 Counter/timer 1 has run down (not implemented)
* 0x00001000 Counter/timer 2 has run down (not implemented)
* 0x00010000 Counter 3 has run down (not implemented)
* Author: Michal Dobes <dobes@tesnet.cz>
*
* Thanks to ZhenGang Shang <ZhenGang.Shang@Advantech.com.cn>
- * for testing and informations.
+ * for testing and information.
*
* hardware driver for Advantech cards:
* card: PCI-1710, PCI-1710HG, PCI-1711, PCI-1713, PCI-1720, PCI-1731
if (ret)
return ret;
- /* intialize all channels to 0V */
+ /* initialize all channels to 0V */
for (i = 0; i < s->n_chan; i++) {
s->readback[i] = s->maxdata / 2;
das08_ao_set_data(dev, i, s->readback[i]);
* This driver is for the Diamond Systems MM-32-AT board
* http://www.diamondsystems.com/products/diamondmm32at
*
- * It is being used on serveral projects inside NASA, without
+ * It is being used on several projects inside NASA, without
* problems so far. For analog input commands, TRIG_EXT is not
* yet supported.
*/
/* start the clock and enable the interrupts */
dmm32at_setaitimer(dev, cmd->scan_begin_arg);
} else {
- /* start the interrups and initiate a single scan */
+ /* start the interrupts and initiate a single scan */
outb(DMM32AT_INTCLK_ADINT, dev->iobase + DMM32AT_INTCLK_REG);
outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG);
}
return insn->n;
}
-/* ripped from mite.h and mite_setup2() to avoid mite dependancy */
+/* ripped from mite.h and mite_setup2() to avoid mite dependency */
#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
#define WENAB (1 << 7) /* window enable */
return insn->n;
}
-/* ripped from mite.h and mite_setup2() to avoid mite dependancy */
+/* ripped from mite.h and mite_setup2() to avoid mite dependency */
#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
#define WENAB (1 << 7) /* window enable */
},
};
-/* ripped from mite.h and mite_setup2() to avoid mite dependancy */
+/* ripped from mite.h and mite_setup2() to avoid mite dependency */
#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
#define WENAB (1 << 7) /* window enable */
if (gxx_status & GI_GATE_ERROR(cidx)) {
ack |= GI_GATE_ERROR_CONFIRM(cidx);
if (gate_error) {
- /*660x don't support automatic acknowledgement
+ /*660x don't support automatic acknowledgment
of gate interrupt via dma read/write
and report bogus gate errors */
if (counter->counter_dev->variant !=
s->insn_bits = pcmuio_dio_insn_bits;
s->insn_config = pcmuio_dio_insn_config;
- /* subdevices 0 and 2 can suppport interrupts */
+ /* subdevices 0 and 2 can support interrupts */
if ((i == 0 && dev->irq) || (i == 2 && devpriv->irq2)) {
/* setup the interrupt subdevice */
dev->read_subdev = s;
/* sending for bytes to module(one byte per cycle iteration) */
for (i = 0; i < 4; i++) {
while (!((inb(usp->usp_iobase + 0)) & TxBE))
- ; /* waits while writting will be allowed */
+ ; /* waits while writing will be allowed */
outb(usp->usp_extra_data[module][i], usp->usp_iobase + 6);
}
outb(i + 1, iobase + 5);
outb('H', iobase + 6); /* requests EEPROM world */
while (!(inb(iobase + 0) & TxBE))
- ; /* waits while writting will be allowed */
+ ; /* waits while writing will be allowed */
outb(0, iobase + 6);
/* waits while reading of two bytes will be allowed */