Fix the error in the axi clock mux setting,
- reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
+ reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
Signed-off-by: Jason Liu <r64343@freescale.com>
/* Set the AXI_ALT_SEL mux. */
reg = __raw_readl(MXC_CCM_CBCDR)
& ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
- reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
+ reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
__raw_writel(reg, MXC_CCM_CBCDR);
/* Set the AXI_SEL mux */