drm/tegra: Prepare DPAUX for supporting generic PM domains

To utilise the DPAUX on Tegra, the SOR power partition must be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework for DPAUX. However, the sequence
for gating/ungating the SOR power partition requires that the DPAUX
reset is asserted/de-asserted at the time the SOR power partition is
gated/ungated, respectively. Now that the reset control core assumes
that resets are exclusive, the Tegra generic PM domain code and the
DPAUX driver cannot request the same reset unless we mark the resets as
shared. Sharing resets will not work in this case because we cannot
guarantee that the reset will be asserted/de-asserted at the appropriate
time. Therefore, given that the Tegra generic PM domain code will handle
the DPAUX reset, do not request the reset in the DPAUX driver if the
DPAUX device has a PM domain associated.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index b0b1f84e98b1abc4a888e0e23aebe5731337fffc..9575114cf71976248f85b04d2733cc8d458aab7d 100644 (file)
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -341,11 +341,14 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
                return -ENXIO;
        }
 
-       dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
-       if (IS_ERR(dpaux->rst)) {
-               dev_err(&pdev->dev, "failed to get reset control: %ld\n",
-                       PTR_ERR(dpaux->rst));
-               return PTR_ERR(dpaux->rst);
+       if (!pdev->dev.pm_domain) {
+               dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
+               if (IS_ERR(dpaux->rst)) {
+                       dev_err(&pdev->dev,
+                               "failed to get reset control: %ld\n",
+                               PTR_ERR(dpaux->rst));
+                       return PTR_ERR(dpaux->rst);
+               }
        }
 
        dpaux->clk = devm_clk_get(&pdev->dev, NULL);
@@ -362,7 +365,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
                return err;
        }
 
-       reset_control_deassert(dpaux->rst);
+       if (dpaux->rst)
+               reset_control_deassert(dpaux->rst);
 
        dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
        if (IS_ERR(dpaux->clk_parent)) {
@@ -440,7 +444,9 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
 disable_parent_clk:
        clk_disable_unprepare(dpaux->clk_parent);
 assert_reset:
-       reset_control_assert(dpaux->rst);
+       if (dpaux->rst)
+               reset_control_assert(dpaux->rst);
+
        clk_disable_unprepare(dpaux->clk);
 
        return err;
@@ -462,7 +468,10 @@ static int tegra_dpaux_remove(struct platform_device *pdev)
        cancel_work_sync(&dpaux->work);
 
        clk_disable_unprepare(dpaux->clk_parent);
-       reset_control_assert(dpaux->rst);
+
+       if (dpaux->rst)
+               reset_control_assert(dpaux->rst);
+
        clk_disable_unprepare(dpaux->clk);
 
        return 0;