KVM: arm64: vgic-v3: Enable trapping of Group-1 system registers

In order to be able to trap Group-1 GICv3 system registers, we need to
set ICH_HCR_EL2.TALL1 before entering the guest. This is conditionally
done after having restored the guest's state, and cleared on exit.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Acked-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 1f458ac6f49446f4872ceddd8743a91ce7801582..6b05d2ac8c5464e0b0f4352203c8618379b3c10d 100644 (file)
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -417,6 +417,7 @@
 
 #define ICH_HCR_EN                     (1 << 0)
 #define ICH_HCR_UIE                    (1 << 1)
+#define ICH_HCR_TALL1                  (1 << 12)
 #define ICH_HCR_EOIcount_SHIFT         27
 #define ICH_HCR_EOIcount_MASK          (0x1f << ICH_HCR_EOIcount_SHIFT)
 

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index f031e8f088aee06291e22603af1f7dbd1a772602..a2a62f030341ffa091f92c4efa7463e1bbb3bea0 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -258,6 +258,9 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
                        cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
                }
        } else {
+               if (static_branch_unlikely(&vgic_v3_cpuif_trap))
+                       write_gicreg(0, ICH_HCR_EL2);
+
                cpu_if->vgic_elrsr = 0xffff;
                cpu_if->vgic_ap0r[0] = 0;
                cpu_if->vgic_ap0r[1] = 0;
@@ -330,6 +333,14 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 
                for (i = 0; i < used_lrs; i++)
                        __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
+       } else {
+               /*
+                * If we need to trap system registers, we must write
+                * ICH_HCR_EL2 anyway, even if no interrupts are being
+                * injected,
+                */
+               if (static_branch_unlikely(&vgic_v3_cpuif_trap))
+                       write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
        }
 
        /*

diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index fac6e23cd0b329fdf690fbacdbc964f652bf27c4..722bdebdfbb5b0bddb7d75af0a945adee2072ed0 100644 (file)
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -21,6 +21,8 @@
 
 #include "vgic.h"
 
+static bool group1_trap;
+
 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
 {
        struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
@@ -258,6 +260,8 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
 
        /* Get the show on the road... */
        vgic_v3->vgic_hcr = ICH_HCR_EN;
+       if (group1_trap)
+               vgic_v3->vgic_hcr |= ICH_HCR_TALL1;
 }
 
 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq)