Merge remote-tracking branch 'drm-intel/for-linux-next'

Conflicts:
	drivers/gpu/drm/i915/i915_reg.h
	drivers/gpu/drm/i915/intel_dp.c

diff --cc drivers/gpu/drm/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
index bdb0d7717bc77937dce3c4de563f1e7066c7bb2e,85b3d5d4deecc57e4f2023078dd53c77d816ff0a..1bddf477304aac69d70c425925b7388764a1f24f
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -233,8 -269,16 +269,15 @@@ static int gen6_ppgtt_init(struct i915_
        /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
         * entries. For aliasing ppgtt support we just steal them at the end for
         * now. */
 -      first_pd_entry_in_global_pt =
 -              gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
 +       first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt);
  
+       if (IS_HASWELL(dev)) {
+               ppgtt->pte_encode = hsw_pte_encode;
+       } else if (IS_VALLEYVIEW(dev)) {
+               ppgtt->pte_encode = byt_pte_encode;
+       } else {
+               ppgtt->pte_encode = gen6_pte_encode;
+       }
        ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
        ppgtt->enable = gen6_ppgtt_enable;
        ppgtt->clear_range = gen6_ppgtt_clear_range;

diff --cc drivers/gpu/drm/i915/i915_reg.h
index 2d6b62e42daf324478ea64bc49e6e722330c3e2b,7af7ae66b3385ece1d108e5b099776e0df5df095..b2954489dbb771ce54abbcd0fc8b3f0866f400f4
--- 1/drivers/gpu/drm/i915/i915_reg.h
--- 2/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@@ -2646,18 -2785,19 +2783,19 @@@
   * which is after the LUTs, so we want the bytes for our color format.
   * For our current usage, this is always 3, one byte for R, G and B.
   */
- #define _PIPEA_GMCH_DATA_M                    0x70050
- #define _PIPEB_GMCH_DATA_M                    0x71050
+ #define _PIPEA_DATA_M_G4X     0x70050
+ #define _PIPEB_DATA_M_G4X     0x71050
  
  /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
 -#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK               (0x3f << 25)
 -#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT      25
 +#define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
 +#define  TU_SIZE_MASK           (0x3f << 25)
+ #define  TU_SIZE_SHIFT                25
  
 -#define   PIPE_GMCH_DATA_M_MASK                       (0xffffff)
 +#define  DATA_LINK_M_N_MASK   (0xffffff)
 +#define  DATA_LINK_N_MAX      (0x800000)
  
- #define _PIPEA_GMCH_DATA_N                    0x70054
- #define _PIPEB_GMCH_DATA_N                    0x71054
+ #define _PIPEA_DATA_N_G4X     0x70054
+ #define _PIPEB_DATA_N_G4X     0x71054
 -#define   PIPE_GMCH_DATA_N_MASK                       (0xffffff)
  
  /*
   * Computing Link M and N values for the Display Port link
@@@ -2670,16 -2810,18 +2808,16 @@@
   * Attributes and VB-ID.
   */
  
- #define _PIPEA_DP_LINK_M                              0x70060
- #define _PIPEB_DP_LINK_M                              0x71060
+ #define _PIPEA_LINK_M_G4X     0x70060
+ #define _PIPEB_LINK_M_G4X     0x71060
 -#define   PIPEA_DP_LINK_M_MASK                        (0xffffff)
  
- #define _PIPEA_DP_LINK_N                              0x70064
- #define _PIPEB_DP_LINK_N                              0x71064
+ #define _PIPEA_LINK_N_G4X     0x70064
+ #define _PIPEB_LINK_N_G4X     0x71064
 -#define   PIPEA_DP_LINK_N_MASK                        (0xffffff)
  
- #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
- #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
- #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
- #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
+ #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
+ #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
+ #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
+ #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
  
  /* Display & cursor control */
  

diff --cc drivers/gpu/drm/i915/intel_crt.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_ddi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index 3d704b706a8d42d974e70f4fa3e095fbcbcdb910,2bb4009b7a6024c67d6653ac9a7f5ce9cc8c50b9..a0035c86af9714e661bf12beffb6a429ca0a1cee
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -755,6 -782,10 +783,8 @@@ found
                               target_clock, adjusted_mode->clock,
                               &pipe_config->dp_m_n);
  
 -      pipe_config->pipe_bpp = bpp;
 -
+       intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
+ 
        return true;
  }
  
@@@ -1379,8 -1400,15 +1399,16 @@@ static void intel_enable_dp(struct inte
        ironlake_edp_panel_on(intel_dp);
        ironlake_edp_panel_vdd_off(intel_dp, true);
        intel_dp_complete_link_train(intel_dp);
 +      intel_dp_stop_link_train(intel_dp);
        ironlake_edp_backlight_on(intel_dp);
+ 
+       if (IS_VALLEYVIEW(dev)) {
+               struct intel_digital_port *dport =
+                       enc_to_dig_port(&encoder->base);
+               int channel = vlv_dport_to_channel(dport);
+ 
+               vlv_wait_port_ready(dev_priv, channel);
+       }
  }
  
  static void intel_pre_enable_dp(struct intel_encoder *encoder)

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dvo.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_hdmi.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_opregion.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_sdvo.c
Simple merge