Merge branch 'master' of git://git.denx.de/u-boot-socfpga

diff --git a/arch/arm/mach-socfpga/include/mach/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h
deleted file mode 100644 (file)
index e8ba901..0000000
--- a/arch/arm/mach-socfpga/include/mach/dwmmc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2013 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef        _SOCFPGA_DWMMC_H_
-#define        _SOCFPGA_DWMMC_H_
-
-int socfpga_dwmmc_init(const void *blob);
-
-#endif /* _SOCFPGA_SDMMC_H_ */

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0acc4d38f558b21b49fc8b23463630b988d..dd05e14c0522e27ea39dd2abcd430a649c0baa13 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -16,7 +16,6 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/system_manager.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
 #include <asm/pl310.h>
@@ -77,7 +76,8 @@ void v7_outer_cache_disable(void)
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+                                const u32 phymode)
 {
        u32 physhift, reset;
 
@@ -98,16 +98,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
 
        /* configure to PHY interface select choosed */
        setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-                    SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+                    phymode << physhift);
 
        /* Release the EMAC controller from reset */
        socfpga_per_reset(reset, 0);
 }
 
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+       if (!phymode)
+               return -EINVAL;
+
+       if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+               return 0;
+       }
+
+       if (!strcmp(phymode, "rgmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+               return 0;
+       }
+
+       if (!strcmp(phymode, "rmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+               return 0;
+       }
+
+       return -EINVAL;
+}
+
 static int socfpga_eth_reset(void)
 {
        const void *fdt = gd->fdt_blob;
        struct fdtdec_phandle_args args;
+       const char *phy_mode;
+       u32 phy_modereg;
        int nodes[2];   /* Max. two GMACs */
        int ret, count;
        int i, node;
@@ -132,7 +157,14 @@ static int socfpga_eth_reset(void)
                        continue;
                }
 
-               dwmac_deassert_reset(args.args[0]);
+               phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+               ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+               if (ret) {
+                       debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+                       continue;
+               }
+
+               dwmac_deassert_reset(args.args[0], phy_modereg);
        }
 
        return 0;

diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h
index 83b1093f11966de4bf0d8b3f533d6128ece2b384..51b262b9b7f8c8760a80684ac03c60e10a568f88 100644 (file)
--- a/board/terasic/sockit/qts/iocsr_config.h
+++ b/board/terasic/sockit/qts/iocsr_config.h
@@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00001000,
        0xA0000034,
        0x0D000001,
-       0x40680208,
-       0x41034051,
-       0x12481A00,
-       0x802080D0,
-       0x34051406,
-       0x01A02490,
-       0x080D0000,
-       0x51406802,
-       0x02490340,
+       0xE0680B2C,
+       0x20834038,
+       0x11441A00,
+       0x80B2C0D0,
+       0x34038E06,
+       0x01A00208,
+       0x2C0D0000,
+       0x38E0680B,
+       0x00208340,
        0xD000001A,
-       0x0680A280,
+       0x0680B2C0,
        0x10040000,
        0x00200000,
        0x10040000,
@@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x00001000,
        0xA0000034,
        0x0D000001,
-       0x40680208,
-       0x49034051,
-       0x12481A02,
-       0x80A280D0,
-       0x34030C06,
+       0xE0680B2C,
+       0x20834038,
+       0x11441A00,
+       0x80B2C0D0,
+       0x34038E06,
        0x01A00040,
-       0x280D0002,
-       0x5140680A,
-       0x02490340,
-       0xD012481A,
-       0x0680A280,
+       0x2C0D0002,
+       0x38E0680B,
+       0x00208340,
+       0xD001041A,
+       0x0680B2C0,
        0x10040000,
        0x00200000,
        0x10040000,
@@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x14F3690D,
        0x1A041414,
        0x00D00000,
-       0x04864000,
-       0x59647A01,
-       0xD32CA3DE,
-       0xF551451E,
-       0x034CD348,
+       0x18864000,
+       0x49247A06,
+       0xABCF23D7,
+       0xF7DE791E,
+       0x0356E388,
        0x821A0000,
        0x0000D000,
-       0x05140680,
-       0xD669A47A,
-       0x1ED32CA3,
-       0x48F55E79,
-       0x00034C92,
+       0x05960680,
+       0xD749247A,
+       0x1EABCF23,
+       0x88F7DE79,
+       0x000356E3,
        0x00080200,
        0x00001000,
        0x00080200,
@@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x14F3690D,
        0x1A041414,
        0x00D00000,
-       0x14864000,
-       0x59647A05,
-       0x9228A3DE,
-       0xF65E791E,
-       0x034CD348,
-       0x821A0186,
+       0x18864000,
+       0x49247A06,
+       0xABCF23D7,
+       0xF7DE791E,
+       0x0356E388,
+       0x821A01C7,
        0x0000D000,
        0x00000680,
-       0xD669A47A,
-       0x1E9228A3,
-       0x48F65E79,
-       0x00034CD3,
+       0xD749247A,
+       0x1EABCF23,
+       0x88F7DE79,
+       0x000356E3,
        0x00080200,
        0x00001000,
        0x00080200,
@@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x14F3690D,
        0x1A041414,
        0x00D00000,
-       0x0C864000,
-       0x79E47A03,
-       0xB2AAA3D1,
-       0xF551451E,
-       0x035CD348,
+       0x18864000,
+       0x49247A06,
+       0xABCF23D7,
+       0xF7DE791E,
+       0x0356E388,
        0x821A0000,
        0x0000D000,
        0x00000680,
-       0xD159647A,
-       0x1ED32CA3,
-       0x48F55145,
-       0x00035CD3,
+       0xD749247A,
+       0x1EABCF23,
+       0x88F7DE79,
+       0x000356E3,
        0x00080200,
        0x00001000,
        0x00080200,
@@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = {
        0x14F1690D,
        0x1A041414,
        0x00D00000,
-       0x04864000,
-       0x69A47A01,
-       0x9228A3D6,
-       0xF65E791E,
-       0x034C9248,
+       0x18864000,
+       0x49247A06,
+       0xABCF23D7,
+       0xF7DE791E,
+       0x0356E388,
        0x821A0000,
        0x0000D000,
        0x00000680,
-       0xDE59647A,
-       0x1ED32CA3,
-       0x48F55E79,
-       0x00034CD3,
+       0xD749247A,
+       0x1EABCF23,
+       0x88F7DE79,
+       0x000356E3,
        0x00080200,
        0x00001000,
        0x00080200,

diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h
index 0ecccbf0622ec8874a9a100f64f58347ccee3de9..820b9fff655663681875c963aa963b5e57d48062 100644 (file)
--- a/board/terasic/sockit/qts/pll_config.h
+++ b/board/terasic/sockit/qts/pll_config.h
@@ -10,13 +10,13 @@
 #define CONFIG_HPS_DBCTRL_STAYOSC1 1
 
 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
@@ -61,7 +61,7 @@
 #define CONFIG_HPS_CLK_OSC2_HZ 25000000
 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125
@@ -69,7 +69,7 @@
 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
 #define CONFIG_HPS_CLK_NAND_HZ 50000000
 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000
-#define CONFIG_HPS_CLK_QSPI_HZ 370000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
 #define CONFIG_HPS_CLK_SPIM_HZ 200000000
 #define CONFIG_HPS_CLK_CAN0_HZ 12500000
 #define CONFIG_HPS_CLK_CAN1_HZ 12500000
@@ -78,8 +78,8 @@
 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000
 
 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1
-#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
-#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
 
 
 #endif /* __SOCFPGA_PLL_CONFIG_H__ */

diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 81c7d8e9a80f9be44f1c18278b264084d6037ffe..769aa77394cf05eada252909a9ddb55cb56e2c4f 100644 (file)
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -32,11 +32,11 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ                    0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE                   1
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        8
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        12
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
@@ -46,7 +46,7 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT         3
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512
 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC                 0
@@ -127,8 +127,8 @@
 
 /* Sequencer defines configuration */
 #define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET     8
-#define CALIB_VFIFO_OFFSET     6
+#define CALIB_LFIFO_OFFSET     12
+#define CALIB_VFIFO_OFFSET     10
 #define ENABLE_SUPER_QUICK_CALIBRATION 0
 #define IO_DELAY_PER_DCHAIN_TAP        25
 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
@@ -147,7 +147,7 @@
 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
 #define MAX_LATENCY_COUNT_WIDTH        5
 #define READ_VALID_FIFO_SIZE   16
-#define REG_FILE_INIT_SEQ_SIGNATURE    0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE    0x5555048c
 #define RW_MGR_MEM_ADDRESS_MIRRORING   0
 #define RW_MGR_MEM_DATA_MASK_WIDTH     4
 #define RW_MGR_MEM_DATA_WIDTH  32
@@ -171,16 +171,16 @@
 const u32 ac_rom_init[] = {
        0x20700000,
        0x20780000,
-       0x10080431,
-       0x10080530,
-       0x10090044,
-       0x100a0008,
+       0x10080471,
+       0x10080570,
+       0x10090006,
+       0x100a0218,
        0x100b0000,
        0x10380400,
-       0x10080449,
-       0x100804c8,
-       0x100a0024,
-       0x10090010,
+       0x10080469,
+       0x100804e8,
+       0x100a0006,
+       0x10090218,
        0x100b0000,
        0x30780000,
        0x38780000,

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index d93600bc49e20866105b767d096b3724ffd80d53..087d6f15f3a23a3dcf5b00a718a17cae4f2bc565 100644 (file)
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y

diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index f77e124ed9b9896f5ed0ac2f0042b69129eb2700..cef644e767330136af79a79f9fcd0209633bdb12 100644 (file)
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y

diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 9c341b6afaca34033c9fd2fcd35a4516cd88651a..c0ffad213b05013f3435c9a16f12b25188a09e7d 100644 (file)
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y

diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 48c7012c752a7385d4e2e515c36db6a21c3cfabf..e01282cda09b2a915dc1c0a62248b4281f28cc07 100644 (file)
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -19,6 +19,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y

diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 6a135041fd84f95b4ffda1bb322c7ad25d4999f0..8feb5a357f3136dff9d8882ff3b44739aeb2dadb 100644 (file)
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y

diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 086070766ac2192e0aa30edec89fa569570ee063..1b3c3dfe97082f8e700e0f9fafe5349c54a355dc 100644 (file)
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_DESIGNWARE_SPI=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_GADGET=y

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 2842fba2fd20a7f0d2a17a0273818873f5d7766b..ec57746b23c6e902007b4066a332d8a7d706d347 100644 (file)
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -17,6 +17,7 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 43a7e7ea3247bb1c3aa91c2da03a317310c723b3..097db81b05131a63d030983def8c593beac0dfe8 100644 (file)
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,7 +6,6 @@
 
 #include <common.h>
 #include <asm/arch/clock_manager.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/system_manager.h>
 #include <dm.h>
 #include <dwmmc.h>

diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index a0161bc7d1c01fd8a39965a7ecb969dfe60c2e3f..153f9f8cd3f3db3229d7742f3c5ff3becb5fe06f 100644 (file)
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -56,7 +56,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 07519c1e6c3be35f87a1a3f399c41a10d2f5e2b8..3e5089256822355e10ed71a428dd90dece8a3ceb 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -93,7 +93,6 @@
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_SF_DEFAULT_SPEED                30000000
-#define CONFIG_SPI_FLASH_BAR
 /*
  * The base address is configurable in QSys, each board must specify the
  * base address based on it's particular FPGA configuration. Please note
@@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #endif
 #define CONFIG_CQSPI_DECODER           0
 #define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH_BAR
 
 /*
  * Designware SPI support

diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index c4c4ecb0e07165ed1c5bbd6389d260a6eee67f41..d7c339e6f82e11efc4d2001ee695eb50fea5bc79 100644 (file)
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -56,7 +56,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \

diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index cbc7396083be802eae5bdb9ae343785148133e66..314b9bfb144c40dc272a8177379bde6a68681173 100644 (file)
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -51,7 +51,7 @@
 
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \

diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 95e7ba61ce2d4602029475ecee52de54f25ecbee..07cfcbfe49f8176c5772ec4a990cb44750359a59 100644 (file)
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -52,7 +52,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \

diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index c32a40a0a580ae76f65670503c28d36bc0409342..02ea0c50a8ca9a0df79cbc9ea56a0888a6419a71 100644 (file)
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -52,7 +52,7 @@
 /* Extra Environment */
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \

diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index 6414eeb91475e3449306bb932a81bba4f3143897..e43b5cf62c1af8002782357f3061fc8d8b024048 100644 (file)
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -55,7 +55,7 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "verify=n\0" \
-       "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
        "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
                "bootm ${loadaddr} - ${fdt_addr}\0" \
        "bootimage=zImage\0" \