drm/i915/bxt: Enable GMBUS IRQ

GMBUS interrupt has been moved to CPU side in BXT.
What this patch does is:
1. Enable GMBUS IRQ in de_post_install function
2. Handle this interrupt as a port interrupt in display irq
   handler

v2: Rebase on top of the for_each_pipe() change adding dev_priv as
    first argument (Damien).
v3: read BXT_DE_PORT_GMBUS IIR flag only on BXT on other platforms
    it's reserved (imre)
v4: (jani)
- remove redundant 'BXT GMBUS' comment
- fix formatting of BXT_DE_PORT_GMBUS definition

Reviewed-by: Satheeshakrishna M <satheeshakrishna.m@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 17a8f8c61753e8c7429574bd94aab353f70445e3..f776584ce363503683198d34b3444a25d9ece422 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2244,6 +2244,11 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
                                found = true;
                        }
 
+                       if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
+                               gmbus_irq_handler(dev);
+                               found = true;
+                       }
+
                        if (!found)
                                DRM_ERROR("Unexpected DE Port interrupt\n");
                }
@@ -3515,13 +3520,16 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
        uint32_t de_pipe_enables;
        int pipe;
-       u32 aux_en = GEN8_AUX_CHANNEL_A;
+       u32 de_port_en = GEN8_AUX_CHANNEL_A;
 
        if (IS_GEN9(dev_priv)) {
                de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
                                  GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
-               aux_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
+               de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
                        GEN9_AUX_CHANNEL_D;
+
+               if (IS_BROXTON(dev_priv))
+                       de_port_en |= BXT_DE_PORT_GMBUS;
        } else
                de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
                                  GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
@@ -3540,7 +3548,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
                                          dev_priv->de_irq_mask[pipe],
                                          de_pipe_enables);
 
-       GEN5_IRQ_INIT(GEN8_DE_PORT_, ~aux_en, aux_en);
+       GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
 }
 
 static int gen8_irq_postinstall(struct drm_device *dev)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ccdbd25b78a681c53fa9b9e737f8e314b97f4444..4b53b2083c7867332962f8ea0dfad65a06c80c6e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5383,6 +5383,7 @@ enum skl_disp_power_wells {
                                         BXT_DE_PORT_HP_DDIB | \
                                         BXT_DE_PORT_HP_DDIC)
 #define  GEN8_PORT_DP_A_HOTPLUG                (1 << 3)
+#define  BXT_DE_PORT_GMBUS             (1 << 1)
 #define  GEN8_AUX_CHANNEL_A            (1 << 0)
 
 #define GEN8_DE_MISC_ISR 0x44460