Add support for the MCSR SPR. This only implements the SPR storage
bits, not actual machine checks.
Signed-off-by: Alexander Graf <agraf@suse.de>
case SPRN_IVOR15:
vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
break;
+ case SPRN_MCSR:
+ vcpu->arch.mcsr &= ~spr_val;
+ break;
default:
emulated = EMULATE_FAIL;
case SPRN_IVOR15:
*spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
break;
+ case SPRN_MCSR:
+ *spr_val = vcpu->arch.mcsr;
+ break;
default:
emulated = EMULATE_FAIL;