ath9k: define correct GPIO numbers and bits mask

Define correct GPIO numbers and MASK bits to indicate the WMAC
GPIO resource.

Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs
which rely on gpiolib framework. But restrict SOC AR9330 only to
access WMAC GPIO which has the same design with the old chips.

Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>

diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index e7a31016f370ade654f6e4fcd05e3adc4595a13e..f14242b3213e033607186ef165872a63bad6b163 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -2385,6 +2385,61 @@ static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
        }
 }
 
+static void ath9k_gpio_cap_init(struct ath_hw *ah)
+{
+       struct ath9k_hw_capabilities *pCap = &ah->caps;
+
+       if (AR_SREV_9271(ah)) {
+               pCap->num_gpio_pins = AR9271_NUM_GPIO;
+               pCap->gpio_mask = AR9271_GPIO_MASK;
+       } else if (AR_DEVID_7010(ah)) {
+               pCap->num_gpio_pins = AR7010_NUM_GPIO;
+               pCap->gpio_mask = AR7010_GPIO_MASK;
+       } else if (AR_SREV_9287(ah)) {
+               pCap->num_gpio_pins = AR9287_NUM_GPIO;
+               pCap->gpio_mask = AR9287_GPIO_MASK;
+       } else if (AR_SREV_9285(ah)) {
+               pCap->num_gpio_pins = AR9285_NUM_GPIO;
+               pCap->gpio_mask = AR9285_GPIO_MASK;
+       } else if (AR_SREV_9280(ah)) {
+               pCap->num_gpio_pins = AR9280_NUM_GPIO;
+               pCap->gpio_mask = AR9280_GPIO_MASK;
+       } else if (AR_SREV_9300(ah)) {
+               pCap->num_gpio_pins = AR9300_NUM_GPIO;
+               pCap->gpio_mask = AR9300_GPIO_MASK;
+       } else if (AR_SREV_9330(ah)) {
+               pCap->num_gpio_pins = AR9330_NUM_GPIO;
+               pCap->gpio_mask = AR9330_GPIO_MASK;
+       } else if (AR_SREV_9340(ah)) {
+               pCap->num_gpio_pins = AR9340_NUM_GPIO;
+               pCap->gpio_mask = AR9340_GPIO_MASK;
+       } else if (AR_SREV_9462(ah)) {
+               pCap->num_gpio_pins = AR9462_NUM_GPIO;
+               pCap->gpio_mask = AR9462_GPIO_MASK;
+       } else if (AR_SREV_9485(ah)) {
+               pCap->num_gpio_pins = AR9485_NUM_GPIO;
+               pCap->gpio_mask = AR9485_GPIO_MASK;
+       } else if (AR_SREV_9531(ah)) {
+               pCap->num_gpio_pins = AR9531_NUM_GPIO;
+               pCap->gpio_mask = AR9531_GPIO_MASK;
+       } else if (AR_SREV_9550(ah)) {
+               pCap->num_gpio_pins = AR9550_NUM_GPIO;
+               pCap->gpio_mask = AR9550_GPIO_MASK;
+       } else if (AR_SREV_9561(ah)) {
+               pCap->num_gpio_pins = AR9561_NUM_GPIO;
+               pCap->gpio_mask = AR9561_GPIO_MASK;
+       } else if (AR_SREV_9565(ah)) {
+               pCap->num_gpio_pins = AR9565_NUM_GPIO;
+               pCap->gpio_mask = AR9565_GPIO_MASK;
+       } else if (AR_SREV_9580(ah)) {
+               pCap->num_gpio_pins = AR9580_NUM_GPIO;
+               pCap->gpio_mask = AR9580_GPIO_MASK;
+       } else {
+               pCap->num_gpio_pins = AR_NUM_GPIO;
+               pCap->gpio_mask = AR_GPIO_MASK;
+       }
+}
+
 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 {
        struct ath9k_hw_capabilities *pCap = &ah->caps;
@@ -2478,20 +2533,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
        else
                pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
 
-       if (AR_SREV_9271(ah))
-               pCap->num_gpio_pins = AR9271_NUM_GPIO;
-       else if (AR_DEVID_7010(ah))
-               pCap->num_gpio_pins = AR7010_NUM_GPIO;
-       else if (AR_SREV_9300_20_OR_LATER(ah))
-               pCap->num_gpio_pins = AR9300_NUM_GPIO;
-       else if (AR_SREV_9287_11_OR_LATER(ah))
-               pCap->num_gpio_pins = AR9287_NUM_GPIO;
-       else if (AR_SREV_9285_12_OR_LATER(ah))
-               pCap->num_gpio_pins = AR9285_NUM_GPIO;
-       else if (AR_SREV_9280_20_OR_LATER(ah))
-               pCap->num_gpio_pins = AR928X_NUM_GPIO;
-       else
-               pCap->num_gpio_pins = AR_NUM_GPIO;
+       ath9k_gpio_cap_init(ah);
 
        if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
                pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 831a54415a2512fe890832dcd6ec688d160b1a7c..c0740d6b3e975d00931b144eb6b36f4ba3207d0f 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -301,6 +301,7 @@ struct ath9k_hw_capabilities {
        u8 max_txchains;
        u8 max_rxchains;
        u8 num_gpio_pins;
+       u32 gpio_mask;
        u8 rx_hp_qdepth;
        u8 rx_lp_qdepth;
        u8 rx_status_len;

diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index c8d35febaf0f7e7ffb2bdc462f2987ab5f1a3896..c06fdb955787a072ba898eb17e7f2f2beb7a9bdf 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -985,6 +985,10 @@
 #define AR_SREV_9561(_ah) \
        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9561))
 
+#define AR_SREV_SOC(_ah) \
+       (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(ah) || \
+        AR_SREV_9561(ah))
+
 /* NOTE: When adding chips newer than Peacock, add chip check here */
 #define AR_SREV_9580_10_OR_LATER(_ah) \
        (AR_SREV_9580(_ah))
@@ -1104,14 +1108,46 @@ enum {
 
 #define AR_PCIE_PHY_REG3                        0x18c08
 
+/* Define correct GPIO numbers and MASK bits to indicate the WMAC
+ * GPIO resource.
+ * Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs
+ * which rely on gpiolib framework. But restrict SOC AR9330 only to
+ * access WMAC GPIO which has the same design with the old chips.
+ */
 #define AR_NUM_GPIO                              14
-#define AR928X_NUM_GPIO                          10
+#define AR9280_NUM_GPIO                          10
 #define AR9285_NUM_GPIO                          12
-#define AR9287_NUM_GPIO                          11
+#define AR9287_NUM_GPIO                          10
 #define AR9271_NUM_GPIO                          16
-#define AR9300_NUM_GPIO                          17
+#define AR9300_NUM_GPIO                          16
+#define AR9330_NUM_GPIO                                 16
+#define AR9340_NUM_GPIO                                 23
+#define AR9462_NUM_GPIO                                 10
+#define AR9485_NUM_GPIO                                 12
+#define AR9531_NUM_GPIO                                 18
+#define AR9550_NUM_GPIO                                 24
+#define AR9561_NUM_GPIO                                 23
+#define AR9565_NUM_GPIO                                 12
+#define AR9580_NUM_GPIO                                 16
 #define AR7010_NUM_GPIO                          16
 
+#define AR_GPIO_MASK                            0x00003FFF
+#define AR9271_GPIO_MASK                        0x0000FFFF
+#define AR9280_GPIO_MASK                        0x000003FF
+#define AR9285_GPIO_MASK                        0x00000FFF
+#define AR9287_GPIO_MASK                        0x000003FF
+#define AR9300_GPIO_MASK                        0x0000F4FF
+#define AR9330_GPIO_MASK                        0x0000F4FF
+#define AR9340_GPIO_MASK                        0x0000000F
+#define AR9462_GPIO_MASK                        0x000003FF
+#define AR9485_GPIO_MASK                        0x00000FFF
+#define AR9531_GPIO_MASK                        0x0000000F
+#define AR9550_GPIO_MASK                        0x0000000F
+#define AR9561_GPIO_MASK                        0x0000000F
+#define AR9565_GPIO_MASK                        0x00000FFF
+#define AR9580_GPIO_MASK                        0x0000F4FF
+#define AR7010_GPIO_MASK                        0x0000FFFF
+
 #define AR_GPIO_IN_OUT                           (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
 #define AR_GPIO_IN_VAL                           0x0FFFC000
 #define AR_GPIO_IN_VAL_S                         14