<&clks 197>, <&clks 107>,
<&clks 0>, <&clks 118>,
<&clks 62>, <&clks 139>,
- <&clks 0>;
+ <&clks 0>, <&clks 156>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
- "rxtx7";
+ "rxtx7", "dma";
status = "disabled";
};
compatible = "fsl,imx6q-esai";
reg = <0x02024000 0x4000>;
interrupts = <0 51 0x04>;
- clocks = <&clks 118>;
+ clocks = <&clks 118>, <&clks 156>;
+ clock-names = "core", "dma";
fsl,esai-dma-events = <24 23>;
fsl,flags = <1>;
status = "disabled";
<&clks IMX6SL_CLK_SPDIF>,
<&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6SL_CLK_IPG>,
- <&clks 0>, <&clks 0>;
+ <&clks 0>, <&clks 0>,
+ <&clks IMX6SL_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
- "rxtx7";
+ "rxtx7", "dma";
status = "disabled";
};
struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
clk_enable(esai->clk);
+ clk_prepare_enable(esai->dmaclk);
if (!cpu_dai->active) {
writel(ESAI_GPIO_ESAI, esai->base + ESAI_PRRC);
writel(ESAI_GPIO_ESAI, esai->base + ESAI_PCRC);
{
struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
+ clk_disable_unprepare(esai->dmaclk);
clk_disable(esai->clk);
}
}
esai->flags = flag;
- esai->clk = devm_clk_get(&pdev->dev, NULL);
+ esai->clk = devm_clk_get(&pdev->dev, "core");
if (IS_ERR(esai->clk)) {
ret = PTR_ERR(esai->clk);
dev_err(&pdev->dev, "Cannot get the clock: %d\n", ret);
}
clk_prepare(esai->clk);
+ esai->dmaclk = devm_clk_get(&pdev->dev, "dma");
+ if (IS_ERR(esai->dmaclk)) {
+ ret = PTR_ERR(esai->dmaclk);
+ dev_err(&pdev->dev, "Cannot get dma clock: %d\n", ret);
+ goto failed_get_resource;
+ }
+
ret = of_address_to_resource(np, 0, &res);
if (ret) {
dev_err(&pdev->dev, "could not determine device resources\n");
struct fsl_esai {
struct clk *clk;
+ struct clk *dmaclk;
void __iomem *base;
int irq;
unsigned int flags;
struct clk *txclk[SPDIF_TXRATE_MAX];
struct clk *rxclk;
struct clk *sysclk;
+ struct clk *dmaclk;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
int ret;
pm_runtime_get_sync(cpu_dai->dev);
+ clk_prepare_enable(spdif_priv->dmaclk);
/* Reset module and interrupts only for first initialization */
if (!cpu_dai->active) {
SCR_LOW_POWER, SCR_LOW_POWER);
}
+ clk_disable_unprepare(spdif_priv->dmaclk);
pm_runtime_put_sync(cpu_dai->dev);
}
return PTR_ERR(spdif_priv->sysclk);
}
+ /* Get dma clock for dma script operation */
+ spdif_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
+ if (IS_ERR(spdif_priv->dmaclk)) {
+ dev_err(&pdev->dev, "no dma clock in devicetree\n");
+ return PTR_ERR(spdif_priv->dmaclk);
+ }
+
/* Select clock source for rx/tx clock */
spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
if (IS_ERR(spdif_priv->rxclk)) {