PCI/ASPM: Add comment about L1 substate latency

Since the exit latencies for L1 substates are not advertised by a device,
it is not clear in spec how to do a L1 substate exit latency check.  We
assume that the L1 exit latencies advertised by a device include L1
substate latencies (and hence do not do any check).  If that is not true,
we should do some sort of check here.

(I'm not clear about what that check should like currently. I'd be glad to
take up any suggestions).

Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index ceb2395c37ae1896277aea1b03ac45347e9a9d69..a9bcd56e41edbd607897b48fac74f054bfebb7f0 100644 (file)
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -403,6 +403,14 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
                 * Check L1 latency.
                 * Every switch on the path to root complex need 1
                 * more microsecond for L1. Spec doesn't mention L0s.
+                *
+                * The exit latencies for L1 substates are not advertised
+                * by a device.  Since the spec also doesn't mention a way
+                * to determine max latencies introduced by enabling L1
+                * substates on the components, it is not clear how to do
+                * a L1 substate exit latency check.  We assume that the
+                * L1 exit latencies advertised by a device include L1
+                * substate latencies (and hence do not do any check).
                 */
                latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
                if ((link->aspm_capable & ASPM_STATE_L1) &&