ok = 1;
claimed = 0;
spin_lock_irqsave(&devpriv->res_spinlock, irqflags);
- for (b = 1, i = 0; (i < NUM_RESOURCES) && (res_mask != 0);
- b <<= 1, i++) {
- if ((res_mask & b) != 0) {
+ for (b = 1, i = 0; (i < NUM_RESOURCES) && res_mask; b <<= 1, i++) {
+ if (res_mask & b) {
res_mask &= ~b;
if (devpriv->res_owner[i] == OWNER_NONE) {
devpriv->res_owner[i] = owner;
claimed |= b;
} else if (devpriv->res_owner[i] != owner) {
- for (b = 1, i = 0; claimed != 0; b <<= 1, i++) {
- if ((claimed & b) != 0) {
+ for (b = 1, i = 0; claimed; b <<= 1, i++) {
+ if (claimed & b) {
devpriv->res_owner[i] =
OWNER_NONE;
claimed &= ~b;
unsigned long irqflags;
spin_lock_irqsave(&devpriv->res_spinlock, irqflags);
- for (b = 1, i = 0; (i < NUM_RESOURCES) && (res_mask != 0);
- b <<= 1, i++) {
- if ((res_mask & b) != 0) {
+ for (b = 1, i = 0; (i < NUM_RESOURCES) && res_mask; b <<= 1, i++) {
+ if (res_mask & b) {
res_mask &= ~b;
if (devpriv->res_owner[i] == owner)
devpriv->res_owner[i] = OWNER_NONE;
* External trigger - for PCI230+ hardware version 2 onwards.
*/
/* Trigger number must be 0. */
- if ((cmd->scan_begin_arg & ~CR_FLAGS_MASK) != 0) {
+ if (cmd->scan_begin_arg & ~CR_FLAGS_MASK) {
cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
~CR_FLAGS_MASK);
err |= -EINVAL;
* The only flags allowed are CR_EDGE and CR_INVERT.
* The CR_EDGE flag is ignored.
*/
- if ((cmd->scan_begin_arg &
- (CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT))) != 0) {
+ if (cmd->scan_begin_arg &
+ (CR_FLAGS_MASK & ~(CR_EDGE | CR_INVERT))) {
cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
CR_FLAGS_MASK &
~(CR_EDGE | CR_INVERT));
}
if (events == 0) {
/* Check for FIFO underrun. */
- if ((dacstat & PCI230P2_DAC_FIFO_UNDERRUN_LATCHED) != 0) {
+ if (dacstat & PCI230P2_DAC_FIFO_UNDERRUN_LATCHED) {
dev_err(dev->class_dev, "AO FIFO underrun\n");
events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
}
}
if (events == 0) {
/* Determine how much room is in the FIFO (in samples). */
- if ((dacstat & PCI230P2_DAC_FIFO_FULL) != 0)
+ if (dacstat & PCI230P2_DAC_FIFO_FULL)
room = PCI230P2_DAC_FIFOROOM_FULL;
- else if ((dacstat & PCI230P2_DAC_FIFO_HALF) != 0)
+ else if (dacstat & PCI230P2_DAC_FIFO_HALF)
room = PCI230P2_DAC_FIFOROOM_HALFTOFULL;
- else if ((dacstat & PCI230P2_DAC_FIFO_EMPTY) != 0)
+ else if (dacstat & PCI230P2_DAC_FIFO_EMPTY)
room = PCI230P2_DAC_FIFOROOM_EMPTY;
else
room = PCI230P2_DAC_FIFOROOM_ONETOHALF;
}
/* Check if FIFO underrun occurred while writing to FIFO. */
dacstat = inw(dev->iobase + PCI230_DACCON);
- if ((dacstat & PCI230P2_DAC_FIFO_UNDERRUN_LATCHED) != 0) {
+ if (dacstat & PCI230P2_DAC_FIFO_UNDERRUN_LATCHED) {
dev_err(dev->class_dev, "AO FIFO underrun\n");
events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
}
}
- if ((events &
- (COMEDI_CB_EOA | COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW)) != 0) {
+ if (events & (COMEDI_CB_EOA | COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW)) {
/* Stopping AO due to completion or error. */
pci230_ao_stop(dev, s);
running = 0;
struct pci230_private *devpriv = dev->private;
unsigned long irqflags;
- if (trig_num != 0)
+ if (trig_num)
return -EINVAL;
spin_lock_irqsave(&devpriv->ao_stop_spinlock, irqflags);
if (subseq_len == 0)
subseq_len = cmd->chanlist_len;
- if ((cmd->chanlist_len % subseq_len) != 0) {
+ if (cmd->chanlist_len % subseq_len) {
dev_dbg(dev->class_dev,
"%s: sequence must repeat exactly\n", __func__);
return -EINVAL;
* the bug, but the second one does, and we can't tell them apart!
*/
if (devpriv->hwver > 0 && devpriv->hwver < 4) {
- if (subseq_len > 1 && CR_CHAN(cmd->chanlist[0]) != 0) {
+ if (subseq_len > 1 && CR_CHAN(cmd->chanlist[0])) {
dev_info(dev->class_dev,
"amplc_pci230: ai_cmdtest: Buggy PCI230+/260+ h/w version %u requires first channel of multi-channel sequence to be 0 (corrected in h/w version 4)\n",
devpriv->hwver);
* convert_arg == (CR_EDGE | CR_INVERT | 0)
* => trigger on -ve edge.
*/
- if ((cmd->convert_arg & CR_FLAGS_MASK) != 0) {
+ if (cmd->convert_arg & CR_FLAGS_MASK) {
/* Trigger number must be 0. */
- if ((cmd->convert_arg & ~CR_FLAGS_MASK) != 0) {
+ if (cmd->convert_arg & ~CR_FLAGS_MASK) {
cmd->convert_arg = COMBINE(cmd->convert_arg, 0,
~CR_FLAGS_MASK);
err |= -EINVAL;
* scan_begin_arg==0 => use PPC0 input -> gate of CT0 -> gate
* of CT2 (sample convert trigger is CT2)
*/
- if ((cmd->scan_begin_arg & ~CR_FLAGS_MASK) != 0) {
+ if (cmd->scan_begin_arg & ~CR_FLAGS_MASK) {
cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
~CR_FLAGS_MASK);
err |= -EINVAL;
}
/* The only flag allowed is CR_EDGE, which is ignored. */
- if ((cmd->scan_begin_arg & CR_FLAGS_MASK & ~CR_EDGE) != 0) {
+ if (cmd->scan_begin_arg & CR_FLAGS_MASK & ~CR_EDGE) {
cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
CR_FLAGS_MASK & ~CR_EDGE);
err |= -EINVAL;
unsigned short triglev;
unsigned short adccon;
- if ((cmd->flags & TRIG_WAKE_EOS) != 0) {
+ if (cmd->flags & TRIG_WAKE_EOS) {
/* Wake at end of scan. */
wake = scanlen - devpriv->ai_scan_pos;
} else {
struct pci230_private *devpriv = dev->private;
unsigned long irqflags;
- if (trig_num != 0)
+ if (trig_num)
return -EINVAL;
spin_lock_irqsave(&devpriv->ai_stop_spinlock, irqflags);
unsigned long irqflags;
unsigned char zgat;
- if (trig_num != 0)
+ if (trig_num)
return -EINVAL;
spin_lock_irqsave(&devpriv->ai_stop_spinlock, irqflags);
conv = PCI230_ADC_TRIG_Z2CT2;
break;
case TRIG_EXT:
- if ((cmd->convert_arg & CR_EDGE) != 0) {
+ if (cmd->convert_arg & CR_EDGE) {
if ((cmd->convert_arg & CR_INVERT) == 0) {
/* Trigger on +ve edge. */
conv = PCI230_ADC_TRIG_EXTP;
}
} else {
/* Backwards compatibility. */
- if (cmd->convert_arg != 0) {
+ if (cmd->convert_arg) {
/* Trigger on +ve edge. */
conv = PCI230_ADC_TRIG_EXTP;
} else {
if (fifoamount == 0) {
/* Read FIFO state. */
status_fifo = inw(dev->iobase + PCI230_ADCCON);
- if ((status_fifo & PCI230_ADC_FIFO_FULL_LATCHED) != 0) {
+ if (status_fifo & PCI230_ADC_FIFO_FULL_LATCHED) {
/*
* Report error otherwise FIFO overruns will go
* unnoticed by the caller.
dev_err(dev->class_dev, "AI FIFO overrun\n");
events |= COMEDI_CB_OVERFLOW | COMEDI_CB_ERROR;
break;
- } else if ((status_fifo & PCI230_ADC_FIFO_EMPTY) != 0) {
+ } else if (status_fifo & PCI230_ADC_FIFO_EMPTY) {
/* FIFO empty. */
break;
- } else if ((status_fifo & PCI230_ADC_FIFO_HALF) != 0) {
+ } else if (status_fifo & PCI230_ADC_FIFO_HALF) {
/* FIFO half full. */
fifoamount = PCI230_ADC_FIFOLEVEL_HALFFULL;
} else {
events |= COMEDI_CB_BLOCK;
}
async->events |= events;
- if ((async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
- COMEDI_CB_OVERFLOW)) != 0) {
+ if (async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
+ COMEDI_CB_OVERFLOW)) {
/* disable hardware conversions */
pci230_ai_stop(dev, s);
} else {
* two.
*/
- if ((valid_status_int & PCI230_INT_ZCLK_CT1) != 0) {
+ if (valid_status_int & PCI230_INT_ZCLK_CT1) {
s = dev->write_subdev;
pci230_handle_ao_nofifo(dev, s);
comedi_event(dev, s);
}
- if ((valid_status_int & PCI230P2_INT_DAC) != 0) {
+ if (valid_status_int & PCI230P2_INT_DAC) {
s = dev->write_subdev;
pci230_handle_ao_fifo(dev, s);
comedi_event(dev, s);
}
- if ((valid_status_int & PCI230_INT_ADC) != 0) {
+ if (valid_status_int & PCI230_INT_ADC) {
s = dev->read_subdev;
pci230_handle_ai(dev, s);
comedi_event(dev, s);
}
}
outw(extfunc, dev->iobase + PCI230P_EXTFUNC);
- if ((extfunc & PCI230P2_EXTFUNC_DACFIFO) != 0) {
+ if (extfunc & PCI230P2_EXTFUNC_DACFIFO) {
/*
* Temporarily enable DAC FIFO, reset it and disable
* FIFO wraparound.