drm/i915/chv: Force clock buffer enables

Try to force the PHY clock buffer enables to make the clock routing
work.

v2: Fix the pipe B case to actually enable CH0 clock buffers

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dba8776474d7e1db7ec7f2f449b5aa2edb0a2b79..4c0d2564467e05e4c7b8dbbfda3ff1f7ee264353 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -881,6 +881,16 @@ enum punit_power_well {
 #define   DPIO_CHV_PROP_COEFF_SHIFT    0
 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
+#define _CHV_CMN_DW5_CH0               0x8114
+#define   CHV_BUFRIGHTENA1_DISABLE     (0 << 20)
+#define   CHV_BUFRIGHTENA1_NORMAL      (1 << 20)
+#define   CHV_BUFRIGHTENA1_FORCE       (3 << 20)
+#define   CHV_BUFRIGHTENA1_MASK                (3 << 20)
+#define   CHV_BUFLEFTENA1_DISABLE      (0 << 22)
+#define   CHV_BUFLEFTENA1_NORMAL       (1 << 22)
+#define   CHV_BUFLEFTENA1_FORCE                (3 << 22)
+#define   CHV_BUFLEFTENA1_MASK         (3 << 22)
+
 #define _CHV_CMN_DW13_CH0              0x8134
 #define _CHV_CMN_DW0_CH1               0x8080
 #define   DPIO_CHV_S1_DIV_SHIFT                21
@@ -895,6 +905,14 @@ enum punit_power_well {
 #define _CHV_CMN_DW1_CH1               0x8084
 #define   DPIO_AFC_RECAL               (1 << 14)
 #define   DPIO_DCLKP_EN                        (1 << 13)
+#define   CHV_BUFLEFTENA2_DISABLE      (0 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_NORMAL       (1 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_FORCE                (3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_MASK         (3 << 17) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_DISABLE     (0 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_NORMAL      (1 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_FORCE       (3 << 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_MASK                (3 << 19) /* CL2 DW1 only */
 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
 
 #define _CHV_CMN_DW19_CH0              0x814c

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 48827db70ef45a5acb642397d22659c039ca9053..398d45a6e071b4ac75c963ecbd69a7e2ac411f32 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2094,6 +2094,25 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
 
        mutex_lock(&dev_priv->dpio_lock);
 
+       /* program left/right clock distribution */
+       if (pipe != PIPE_B) {
+               val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+               val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+               if (ch == DPIO_CH0)
+                       val |= CHV_BUFLEFTENA1_FORCE;
+               if (ch == DPIO_CH1)
+                       val |= CHV_BUFRIGHTENA1_FORCE;
+               vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+       } else {
+               val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+               val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+               if (ch == DPIO_CH0)
+                       val |= CHV_BUFLEFTENA2_FORCE;
+               if (ch == DPIO_CH1)
+                       val |= CHV_BUFRIGHTENA2_FORCE;
+               vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+       }
+
        /* program clock channel usage */
        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
        val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index bc5c142b59cabaa1061253d8ec426acf8ac52e27..70a89cc39f2c40b76fdc93c8b1d5a5c45691f93b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1242,6 +1242,25 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
 
        mutex_lock(&dev_priv->dpio_lock);
 
+       /* program left/right clock distribution */
+       if (pipe != PIPE_B) {
+               val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
+               val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
+               if (ch == DPIO_CH0)
+                       val |= CHV_BUFLEFTENA1_FORCE;
+               if (ch == DPIO_CH1)
+                       val |= CHV_BUFRIGHTENA1_FORCE;
+               vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
+       } else {
+               val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
+               val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
+               if (ch == DPIO_CH0)
+                       val |= CHV_BUFLEFTENA2_FORCE;
+               if (ch == DPIO_CH1)
+                       val |= CHV_BUFRIGHTENA2_FORCE;
+               vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
+       }
+
        /* program clock channel usage */
        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
        val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;