}
MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
- .boot_params = PLAT_PHYS_OFFSET + 0x100,
+ .atag_offset = 0x100,
+ .fixup = msm7x30_fixup,
+ .reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
MACHINE_END
MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
- .boot_params = PLAT_PHYS_OFFSET + 0x100,
+ .atag_offset = 0x100,
+ .fixup = msm7x30_fixup,
+ .reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
MACHINE_END
MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
- .boot_params = PLAT_PHYS_OFFSET + 0x100,
+ .atag_offset = 0x100,
+ .fixup = msm7x30_fixup,
+ .reserve = msm7x30_reserve,
.map_io = msm7x30_map_io,
.init_irq = msm7x30_init_irq,
.init_machine = msm7x30_init,
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
+#include <linux/memblock.h>
+ #include <linux/irqdomain.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
{
}
+ #ifdef CONFIG_OF
+ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
+ {}
+ };
+
+ static struct of_device_id msm_dt_gic_match[] __initdata = {
+ { .compatible = "qcom,msm-8660-qgic", },
+ {}
+ };
+
+ static void __init msm8x60_dt_init(void)
+ {
+ struct device_node *node;
+
+ node = of_find_matching_node_by_address(NULL, msm_dt_gic_match,
+ MSM8X60_QGIC_DIST_PHYS);
+ if (node)
+ irq_domain_add_simple(node, GIC_SPI_START);
+
+ if (of_machine_is_compatible("qcom,msm8660-surf")) {
+ printk(KERN_INFO "Init surf UART registers\n");
+ msm8x60_init_uart12dm();
+ }
+
+ of_platform_populate(NULL, of_default_bus_match_table,
+ msm_auxdata_lookup, NULL);
+ }
+
+ static const char *msm8x60_fluid_match[] __initdata = {
+ "qcom,msm8660-fluid",
+ "qcom,msm8660-surf",
+ NULL
+ };
+ #endif /* CONFIG_OF */
+
MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
+ .fixup = msm8x60_fixup,
+ .reserve = msm8x60_reserve,
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
+
+ #ifdef CONFIG_OF
+ /* TODO: General device tree support for all MSM. */
+ DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
++ .fixup = msm8x60_fixup,
++ .reserve = msm8x60_reserve,
+ .map_io = msm8x60_map_io,
+ .init_irq = msm8x60_init_irq,
+ .init_machine = msm8x60_dt_init,
+ .timer = &msm_timer,
+ .dt_compat = msm8x60_fluid_match,
+ MACHINE_END
+ #endif /* CONFIG_OF */
#ifndef __MACH_MXS_GPIO_H__
#define __MACH_MXS_GPIO_H__
- #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
-#include <asm-generic/gpio.h>
--
- #define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
-/* use gpiolib dispatchers */
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq __gpio_to_irq
--
#endif /* __MACH_MXS_GPIO_H__ */
- # Note: the following conditions must always be true:
- # ZRELADDR == virt_to_phys(TEXTADDR)
- # PARAMS_PHYS must be within 4MB of ZRELADDR
- # INITRD_PHYS must be in RAM
-
- ifdef CONFIG_MACH_U300_SINGLE_RAM
- zreladdr-y += 0x28E08000
- params_phys-y := 0x28E00100
- else
- zreladdr-y += 0x48008000
- params_phys-y := 0x48000100
- endif
-
- zreladdr-y := 0x48008000
++ zreladdr-y += 0x48008000
+ params_phys-y := 0x48000100
# This isn't used.
- #initrd_phys-y := 0x29800000
+ #initrd_phys-y := 0x48800000
* code will have already disabled interrupts
*/
for (;;) {
- /*
- * here's the WFI
- */
- asm(".word 0xe320f003\n"
- :
- :
- : "memory", "cc");
+ wfi();
- if (pen_release == cpu) {
+ if (pen_release == cpu_logical_map(cpu)) {
/*
* OK, proper wakeup, we're done
*/
}
#ifdef CONFIG_MMU
- /* Sanity check size */
- #if (CONSISTENT_DMA_SIZE % SZ_2M)
- #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
- #endif
- #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
- #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PMD_SHIFT)
- #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PMD_SHIFT)
-
+ #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PGDIR_SHIFT)
++#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
/*
* These are the page tables (2MB each) covering uncached, DMA consistent allocations
#include <linux/spinlock.h>
#include <mach/hardware.h>
-#include <asm-generic/gpio.h>
-
-/* use gpiolib dispatchers */
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq __gpio_to_irq
-
- /* There's a off-by-one betweem the gpio bank number and the gpiochip */
- /* range e.g. GPIO_1_5 is gpio 5 under linux */
- #define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
-
- #define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
- #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
-
#endif