m68knommu: make ColdFire Pin Assignment register definitions absolute addresses

Make all definitions of the ColdFire Pin Assignment registers absolute
addresses. Currently some are relative to the MBAR peripheral region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 02a91f489cbf48da87c78a424eadbf8ad9cc79e2..c78ff10c015388439cb62a7aca599f9d7c4c58c8 100644 (file)
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -85,9 +85,9 @@
 #define        MCFSIM_DMCR             0xc6            /* Default control */
 
 #ifdef CONFIG_M5206e
-#define        MCFSIM_PAR              0xca            /* Pin Assignment reg (r/w) */
+#define        MCFSIM_PAR              (MCF_MBAR + 0xca)       /* Pin Assignment */
 #else
-#define        MCFSIM_PAR              0xcb            /* Pin Assignment reg (r/w) */
+#define        MCFSIM_PAR              (MCF_MBAR + 0xcb)       /* Pin Assignment */
 #endif
 
 #define        MCFTIMER_BASE1          (MCF_MBAR + 0x100)      /* Base of TIMER1 */

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 7229fd8723481a5bff7c3b175bdaf16a8dbc63ce..6e2bb0c571977f469674d9d602b328900b359345 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -29,7 +29,7 @@
 #define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog srv */
-#define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
+#define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
 #define        MCFSIM_IPR              (MCF_MBAR + 0x40)       /* Interrupt Pending */

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index a328e1806febe25a53a892363a0a5fe88e78e3e8..7d89d86144af0e9c7b57735972f46bb016c6c3cf 100644 (file)
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -27,7 +27,7 @@
 #define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
-#define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
+#define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/

diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index 023f5f64ccd596fbadb5dadaab1db1b012c32762..51111afc79260a99a6204c3bbac087b4bf198d51 100644 (file)
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -27,7 +27,7 @@
 #define        MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
 #define        MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
 #define        MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
-#define        MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
+#define        MCFSIM_PAR              (MCF_MBAR + 0x04)       /* Pin Assignment */
 #define        MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define        MCFSIM_PLLCR            0x08            /* PLL Control Reg*/
 #define        MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/