sh: hwblk for sh7722

This patch contains the sh7722 specific hwblk implementation.

Hwblk ids are added to the processor specific header file,
module stop bits and areas are kept track of as hwblks,
clocks are converted to make use of the shared hwblk code.
Code to determine allowed sleep modes is also added.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index 738ea43c5038d72613d940126f2fde0dddbd0aa2..48560407cbe1c92acff99ff7fb858a4f5b1172a8 100644 (file)
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -221,4 +221,18 @@ enum {
        GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYOUT5_IN5,
 };
 
+enum {
+       HWBLK_UNKNOWN = 0,
+       HWBLK_TLB, HWBLK_IC, HWBLK_OC, HWBLK_URAM, HWBLK_XYMEM,
+       HWBLK_INTC, HWBLK_DMAC, HWBLK_SHYWAY, HWBLK_HUDI,
+       HWBLK_UBC, HWBLK_TMU, HWBLK_CMT, HWBLK_RWDT, HWBLK_FLCTL,
+       HWBLK_SCIF0, HWBLK_SCIF1, HWBLK_SCIF2, HWBLK_SIO,
+       HWBLK_SIOF0, HWBLK_SIOF1, HWBLK_IIC, HWBLK_RTC,
+       HWBLK_TPU, HWBLK_IRDA, HWBLK_SDHI, HWBLK_SIM, HWBLK_KEYSC,
+       HWBLK_TSIF, HWBLK_USBF, HWBLK_2DG, HWBLK_SIU, HWBLK_VOU,
+       HWBLK_JPU, HWBLK_BEU, HWBLK_CEU, HWBLK_VEU, HWBLK_VPU,
+       HWBLK_LCDC,
+       HWBLK_NR,
+};
+
 #endif /* __ASM_SH7722_H__ */

diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index ebdd391d5f429f115aaf3d23036283cd80f4ba9c..3cafda696378b7989702a29fde854e41f3778aa4 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -25,7 +25,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7780)    := clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)     := clock-sh7785.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7786)     := clock-sh7786.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)     := clock-sh7343.o
-clock-$(CONFIG_CPU_SUBTYPE_SH7722)     := clock-sh7722.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7722)     := clock-sh7722.o hwblk-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7723)     := clock-sh7723.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7724)     := clock-sh7724.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7366)     := clock-sh7366.o

diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 40f859354f793507c1a0feb7899f4840570f00b8..1fa9e1dd1cc8e790d5ac5836cd29e214013e63bb 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -22,6 +22,8 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <asm/clock.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7722.h>
 
 /* SH7722 registers */
 #define FRQCR          0xa4150000
@@ -140,35 +142,37 @@ struct clk div6_clks[] = {
        SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 };
 
-#define MSTP(_str, _parent, _reg, _bit, _flags) \
-  SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
+#define R_CLK &r_clk
+#define P_CLK &div4_clks[DIV4_P]
+#define B_CLK &div4_clks[DIV4_B]
+#define U_CLK &div4_clks[DIV4_U]
 
 static struct clk mstp_clks[] = {
-       MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
-       MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
-       MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
-       MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
-       MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
-       MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
-       MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
-       MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
-       MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
-
-       MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
-       MSTP("rtc0", &r_clk, MSTPCR1, 8, 0),
-
-       MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
-       MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
-       MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
-       MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
-       MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
-       MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
-       MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
-       MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
-       MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
-       MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
-       MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
-       MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
+       SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT),
+       SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT),
+       SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0),
+       SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0),
+       SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
+       SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
+       SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0),
+       SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0),
+       SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0),
+
+       SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
+       SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
+
+       SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0),
+       SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
+       SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0),
+       SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
+       SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
+       SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
+       SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, CLK_ENABLE_ON_INIT),
+       SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
+       SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
+       SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, CLK_ENABLE_ON_INIT),
+       SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, CLK_ENABLE_ON_INIT),
+       SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0),
 };
 
 int __init arch_clk_init(void)
@@ -191,7 +195,7 @@ int __init arch_clk_init(void)
                ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
        if (!ret)
-               ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
+               ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 
        return ret;
 }

diff --git a/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
new file mode 100644 (file)
index 0000000..00a1c02
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
@@ -0,0 +1,106 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/hwblk-sh7722.c
+ *
+ * SH7722 hardware block support
+ *
+ * Copyright (C) 2009 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <asm/suspend.h>
+#include <asm/hwblk.h>
+#include <cpu/sh7722.h>
+
+/* SH7722 registers */
+#define MSTPCR0                0xa4150030
+#define MSTPCR1                0xa4150034
+#define MSTPCR2                0xa4150038
+
+/* SH7722 Power Domains */
+enum { CORE_AREA, SUB_AREA, CORE_AREA_BM };
+static struct hwblk_area sh7722_hwblk_area[] = {
+       [CORE_AREA] = HWBLK_AREA(0, 0),
+       [CORE_AREA_BM] = HWBLK_AREA(HWBLK_AREA_FLAG_PARENT, CORE_AREA),
+       [SUB_AREA] = HWBLK_AREA(0, 0),
+};
+
+/* Table mapping HWBLK to Module Stop Bit and Power Domain */
+static struct hwblk sh7722_hwblk[HWBLK_NR] = {
+       [HWBLK_TLB] = HWBLK(MSTPCR0, 31, CORE_AREA),
+       [HWBLK_IC] = HWBLK(MSTPCR0, 30, CORE_AREA),
+       [HWBLK_OC] = HWBLK(MSTPCR0, 29, CORE_AREA),
+       [HWBLK_URAM] = HWBLK(MSTPCR0, 28, CORE_AREA),
+       [HWBLK_XYMEM] = HWBLK(MSTPCR0, 26, CORE_AREA),
+       [HWBLK_INTC] = HWBLK(MSTPCR0, 22, CORE_AREA),
+       [HWBLK_DMAC] = HWBLK(MSTPCR0, 21, CORE_AREA_BM),
+       [HWBLK_SHYWAY] = HWBLK(MSTPCR0, 20, CORE_AREA),
+       [HWBLK_HUDI] = HWBLK(MSTPCR0, 19, CORE_AREA),
+       [HWBLK_UBC] = HWBLK(MSTPCR0, 17, CORE_AREA),
+       [HWBLK_TMU] = HWBLK(MSTPCR0, 15, CORE_AREA),
+       [HWBLK_CMT] = HWBLK(MSTPCR0, 14, SUB_AREA),
+       [HWBLK_RWDT] = HWBLK(MSTPCR0, 13, SUB_AREA),
+       [HWBLK_FLCTL] = HWBLK(MSTPCR0, 10, CORE_AREA),
+       [HWBLK_SCIF0] = HWBLK(MSTPCR0, 7, CORE_AREA),
+       [HWBLK_SCIF1] = HWBLK(MSTPCR0, 6, CORE_AREA),
+       [HWBLK_SCIF2] = HWBLK(MSTPCR0, 5, CORE_AREA),
+       [HWBLK_SIO] = HWBLK(MSTPCR0, 3, CORE_AREA),
+       [HWBLK_SIOF0] = HWBLK(MSTPCR0, 2, CORE_AREA),
+       [HWBLK_SIOF1] = HWBLK(MSTPCR0, 1, CORE_AREA),
+
+       [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
+       [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
+
+       [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
+       [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
+       [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
+       [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
+       [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
+       [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
+       [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
+       [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
+       [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
+       [HWBLK_JPU] = HWBLK(MSTPCR2, 6, CORE_AREA_BM),
+       [HWBLK_VOU] = HWBLK(MSTPCR2, 5, CORE_AREA_BM),
+       [HWBLK_BEU] = HWBLK(MSTPCR2, 4, CORE_AREA_BM),
+       [HWBLK_CEU] = HWBLK(MSTPCR2, 3, CORE_AREA_BM),
+       [HWBLK_VEU] = HWBLK(MSTPCR2, 2, CORE_AREA_BM),
+       [HWBLK_VPU] = HWBLK(MSTPCR2, 1, CORE_AREA_BM),
+       [HWBLK_LCDC] = HWBLK(MSTPCR2, 0, CORE_AREA_BM),
+};
+
+static struct hwblk_info sh7722_hwblk_info = {
+       .areas = sh7722_hwblk_area,
+       .nr_areas = ARRAY_SIZE(sh7722_hwblk_area),
+       .hwblks = sh7722_hwblk,
+       .nr_hwblks = ARRAY_SIZE(sh7722_hwblk),
+};
+
+int arch_hwblk_sleep_mode(void)
+{
+       if (!sh7722_hwblk_area[CORE_AREA].cnt)
+               return SUSP_SH_STANDBY | SUSP_SH_SF;
+
+       if (!sh7722_hwblk_area[CORE_AREA_BM].cnt)
+               return SUSP_SH_SLEEP | SUSP_SH_SF;
+
+       return SUSP_SH_SLEEP;
+}
+
+int __init arch_hwblk_init(void)
+{
+       return hwblk_register(&sh7722_hwblk_info);
+}