ARM: l2c: fix dependencies on PL310 errata symbols

A number of configurations spit out warnings similar to:

warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct dependencies (CACHE_L2X0)
warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_727915 which has unmet direct dependencies (CACHE_L2X0)

Clean up the dependencies here:
* PL310 symbols should only be selected when CACHE_L2X0 is enabled.
* Since the cache-l2x0 code detects PL310 presence at runtime, and we will
  eventually get rid of CACHE_PL310, surround these errata options with an
  if CACHE_L2X0 conditional rather than repeating the dependency against
  each.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 8d42eab76d53d758590a80b97da11fbe0c376be7..606b52680f6a9447d91764d91e3d979fd5c5b74b 100644 (file)
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -738,9 +738,9 @@ config SOC_IMX6
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
        select MFD_SYSCON
-       select PL310_ERRATA_588369 if CACHE_PL310
-       select PL310_ERRATA_727915 if CACHE_PL310
-       select PL310_ERRATA_769419 if CACHE_PL310
+       select PL310_ERRATA_588369 if CACHE_L2X0
+       select PL310_ERRATA_727915 if CACHE_L2X0
+       select PL310_ERRATA_769419 if CACHE_L2X0
 
 config SOC_IMX6Q
        bool "i.MX6 Quad/DualLite support"
@@ -775,9 +775,9 @@ config SOC_VF610
        select ARM_GIC
        select PINCTRL_VF610
        select VF_PIT_TIMER
-       select PL310_ERRATA_588369 if CACHE_PL310
-       select PL310_ERRATA_727915 if CACHE_PL310
-       select PL310_ERRATA_769419 if CACHE_PL310
+       select PL310_ERRATA_588369 if CACHE_L2X0
+       select PL310_ERRATA_727915 if CACHE_L2X0
+       select PL310_ERRATA_769419 if CACHE_L2X0
 
        help
          This enable support for Freescale Vybrid VF610 processor.

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0ba482638ebfd1f72c4ad189834ea969cc1f510c..2ff3f23e31b0eac4f15c2fc45520b4bf8ec6b55a 100644 (file)
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -32,8 +32,8 @@ config ARCH_OMAP4
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select OMAP_INTERCONNECT
-       select PL310_ERRATA_588369
-       select PL310_ERRATA_727915
+       select PL310_ERRATA_588369 if CACHE_L2X0
+       select PL310_ERRATA_727915 if CACHE_L2X0
        select PM_OPP if PM
        select PM_RUNTIME if CPU_IDLE
        select ARM_ERRATA_754322

diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index abf9ee9bbc3f445c182e4893a8d0f1f9da3f4e9b..1831e96117614e4a36f2d7e56223bff051326aaf 100644 (file)
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -11,8 +11,8 @@ menuconfig ARCH_STI
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
        select ARM_ERRATA_775420
-       select PL310_ERRATA_753970 if CACHE_PL310
-       select PL310_ERRATA_769419 if CACHE_PL310
+       select PL310_ERRATA_753970 if CACHE_L2X0
+       select PL310_ERRATA_769419 if CACHE_L2X0
        help
          Include support for STiH41x SOCs like STiH415/416 using the device tree
          for discovery

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index b41a42da150539b35a3a6c1b441511db15c5054f..86f5372773838970d452920df36f0dc9fc11572b 100644 (file)
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -16,7 +16,7 @@ config ARCH_U8500
        select PINCTRL
        select PINCTRL_ABX500
        select PINCTRL_NOMADIK
-       select PL310_ERRATA_753970 if CACHE_PL310
+       select PL310_ERRATA_753970 if CACHE_L2X0
        help
          Support for ST-Ericsson's Ux500 architecture
 

diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 90249cfc37b32fd29b11cbfae64ca3c51df08da5..a423de4724abdc2076830d6f0c05edb6d9e0df2a 100644 (file)
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -44,7 +44,7 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
        bool "Enable A5 and A9 only errata work-arounds"
        default y
        select ARM_ERRATA_720789
-       select PL310_ERRATA_753970 if CACHE_PL310
+       select PL310_ERRATA_753970 if CACHE_L2X0
        help
          Provides common dependencies for Versatile Express platforms
          based on Cortex-A5 and Cortex-A9 processors. In order to

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index eda0dd0ab97bf02bc6759b2018ae05818d4006c3..c348eaee7ee29df402ce9103a94174cbb1883213 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -889,9 +889,10 @@ config CACHE_L2X0
        help
          This option enables the L2x0 PrimeCell.
 
+if CACHE_L2X0
+
 config CACHE_PL310
        bool
-       depends on CACHE_L2X0
        default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
        help
          This option enables optimisations for the PL310 cache
@@ -899,7 +900,6 @@ config CACHE_PL310
 
 config PL310_ERRATA_588369
        bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
-       depends on CACHE_L2X0
        help
           The PL310 L2 cache controller implements three types of Clean &
           Invalidate maintenance operations: by Physical Address
@@ -912,7 +912,6 @@ config PL310_ERRATA_588369
 
 config PL310_ERRATA_727915
        bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
-       depends on CACHE_L2X0
        help
          PL310 implements the Clean & Invalidate by Way L2 cache maintenance
          operation (offset 0x7FC). This operation runs in background so that
@@ -923,7 +922,6 @@ config PL310_ERRATA_727915
 
 config PL310_ERRATA_753970
        bool "PL310 errata: cache sync operation may be faulty"
-       depends on CACHE_PL310
        help
          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
 
@@ -938,7 +936,6 @@ config PL310_ERRATA_753970
 
 config PL310_ERRATA_769419
        bool "PL310 errata: no automatic Store Buffer drain"
-       depends on CACHE_L2X0
        help
          On revisions of the PL310 prior to r3p2, the Store Buffer does
          not automatically drain. This can cause normal, non-cacheable
@@ -948,6 +945,8 @@ config PL310_ERRATA_769419
          on systems with an outer cache, the store buffer is drained
          explicitly.
 
+endif
+
 config CACHE_TAUROS2
        bool "Enable the Tauros2 L2 cache controller"
        depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)