Merge tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk...

Merge "ARM: EXYNOS: dts for 4.6, 2nd pull" from Krzysztof Kozlowski:

Samsung DeviceTree updates and improvements for v4.6, second round:
1. Split common reboot/poweroff node to separate DTSI.
2. Don't overheat Odroid XU3 by cooling CPU with cpufreq.

* tag 'samsung-dt-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
  ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
  ARM: dts: exynos: Add cooling levels for Exynos5420 CPUs
  ARM: dts: exynos: Move syscon reboot/poweroff to common dtsi

diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
new file mode 100644 (file)
index 0000000..09a2040
--- /dev/null
+++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+       soc {
+               compatible = "simple-bus";
+
+               poweroff: syscon-poweroff {
+                       compatible = "syscon-poweroff";
+                       regmap = <&pmu_system_controller>;
+                       offset = <0x330C>; /* PS_HOLD_CONTROL */
+                       mask = <0x5200>; /* reset value */
+               };
+
+               reboot: syscon-reboot {
+                       compatible = "syscon-reboot";
+                       regmap = <&pmu_system_controller>;
+                       offset = <0x0400>; /* SWRESET */
+                       mask = <0x1>;
+               };
+       };
+};

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf4803b2a659f4825f1df00d0674b2f3..d9c221517935bd40f6f56877d638395cd3447dac 100644 (file)
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -19,6 +19,7 @@
 
 #include "skeleton.dtsi"
 #include "exynos4-cpu-thermal.dtsi"
+#include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos3250.h>
 
 / {
@@ -152,20 +153,6 @@
                        interrupt-parent = <&gic>;
                };
 
-               poweroff: syscon-poweroff {
-                       compatible = "syscon-poweroff";
-                       regmap = <&pmu_system_controller>;
-                       offset = <0x330C>; /* PS_HOLD_CONTROL */
-                       mask = <0x5200>; /* Reset value */
-               };
-
-               reboot: syscon-reboot {
-                       compatible = "syscon-reboot";
-                       regmap = <&pmu_system_controller>;
-                       offset = <0x0400>; /* SWRESET */
-                       mask = <0x1>;
-               };
-
                mipi_phy: video-phy@10020710 {
                        compatible = "samsung,s5pv210-mipi-video-phy";
                        #phy-cells = <1>;

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index ca621a92319e6e2cfb62a607b6a8b1b0998c6e67..5456094d2f45fa215d6ad860c5ceb9521cf7841d 100644 (file)
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -22,6 +22,7 @@
 #include <dt-bindings/clock/exynos4.h>
 #include <dt-bindings/clock/exynos-audss-clk.h>
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 
 / {
        interrupt-parent = <&gic>;
@@ -163,20 +164,6 @@
                interrupt-parent = <&gic>;
        };
 
-       poweroff: syscon-poweroff {
-               compatible = "syscon-poweroff";
-               regmap = <&pmu_system_controller>;
-               offset = <0x330C>; /* PS_HOLD_CONTROL */
-               mask = <0x5200>; /* reset value */
-       };
-
-       reboot: syscon-reboot {
-               compatible = "syscon-reboot";
-               regmap = <&pmu_system_controller>;
-               offset = <0x0400>; /* SWRESET */
-               mask = <0x1>;
-       };
-
        dsi_0: dsi@11C80000 {
                compatible = "samsung,exynos4210-mipi-dsi";
                reg = <0x11C80000 0x10000>;

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index b61d1f6375104ba4ca7ac9e4ad1061aa040fdf03..92313cac035e4b9e818afad1e6ce229c468d1e2a 100644 (file)
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 
 / {
        interrupt-parent = <&gic>;
@@ -93,20 +94,6 @@
                status = "disabled";
        };
 
-       poweroff: syscon-poweroff {
-               compatible = "syscon-poweroff";
-               regmap = <&pmu_system_controller>;
-               offset = <0x330C>; /* PS_HOLD_CONTROL */
-               mask = <0x5200>; /* reset value */
-       };
-
-       reboot: syscon-reboot {
-               compatible = "syscon-reboot";
-               regmap = <&pmu_system_controller>;
-               offset = <0x0400>; /* SWRESET */
-               mask = <0x1>;
-       };
-
        fimd: fimd@14400000 {
                compatible = "samsung,exynos5250-fimd";
                interrupt-parent = <&combiner>;

diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index f3490f5673449440b353ef9644d5fc944c545c4c..fa558674ac7639a7aaae36860862e7002abb659c 100644 (file)
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include "skeleton.dtsi"
+#include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
 
 / {
@@ -117,20 +118,6 @@
                        reg = <0x10040000 0x5000>;
                };
 
-               poweroff: syscon-poweroff {
-                       compatible = "syscon-poweroff";
-                       regmap = <&pmu_system_controller>;
-                       offset = <0x330C>; /* PS_HOLD_CONTROL */
-                       mask = <0x5200>; /* reset value */
-               };
-
-               reboot: syscon-reboot {
-                       compatible = "syscon-reboot";
-                       regmap = <&pmu_system_controller>;
-                       offset = <0x0400>; /* SWRESET */
-                       mask = <0x1>;
-               };
-
                mct: mct@101C0000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x101C0000 0xB00>;

diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 261d25173f61872edcf6675e3a9edce66b19b476..5c052d7ff55460d2a965c5ed55e20e475ed1b24c 100644 (file)
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -33,6 +33,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu1: cpu@1 {
@@ -42,6 +45,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu2: cpu@2 {
@@ -51,6 +57,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu3: cpu@3 {
@@ -60,6 +69,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu4: cpu@100 {
@@ -70,6 +82,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu5: cpu@101 {
@@ -79,6 +94,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu6: cpu@102 {
@@ -88,6 +106,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu7: cpu@103 {
@@ -97,6 +118,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <7>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
        };
 };

diff --git a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi
index 2b289d7c0d13ddda8c8a19f93f1b8d14f4812ac5..3e4c4ad96d6379a733177e52d3c565f3a62d4ae7 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi
@@ -16,7 +16,7 @@
        thermal-zones {
                cpu0_thermal: cpu0-thermal {
                        thermal-sensors = <&tmu_cpu0 0>;
-                       polling-delay-passive = <0>;
+                       polling-delay-passive = <250>;
                        polling-delay = <0>;
                        trips {
                                cpu_alert0: cpu-alert-0 {
@@ -39,6 +39,23 @@
                                        hysteresis = <0>; /* millicelsius */
                                        type = "critical";
                                };
+                               /*
+                                * Exyunos542x support only 4 trip-points
+                                * so for these polling mode is required.
+                                * Start polling at temperature level of last
+                                * interrupt-driven trip: cpu_alert2
+                                */
+                               cpu_alert3: cpu-alert-3 {
+                                       temperature = <70000>; /* millicelsius */
+                                       hysteresis = <10000>; /* millicelsius */
+                                       type = "passive";
+                               };
+                               cpu_alert4: cpu-alert-4 {
+                                       temperature = <85000>; /* millicelsius */
+                                       hysteresis = <10000>; /* millicelsius */
+                                       type = "passive";
+                               };
+
                        };
                        cooling-maps {
                                map0 {
@@ -53,6 +70,33 @@
                                     trip = <&cpu_alert2>;
                                     cooling-device = <&fan0 2 3>;
                                };
+                               /*
+                                * When reaching cpu_alert3, reduce CPU
+                                * by 2 steps. On Exynos5422/5800 that would
+                                * be: 1500 MHz and 1100 MHz.
+                                */
+                               map3 {
+                                    trip = <&cpu_alert3>;
+                                    cooling-device = <&cpu0 0 2>;
+                               };
+                               map4 {
+                                    trip = <&cpu_alert3>;
+                                    cooling-device = <&cpu4 0 2>;
+                               };
+
+                               /*
+                                * When reaching cpu_alert4, reduce CPU
+                                * further, down to 600 MHz (11 steps for big,
+                                * 7 steps for LITTLE).
+                                */
+                               map5 {
+                                    trip = <&cpu_alert4>;
+                                    cooling-device = <&cpu0 3 7>;
+                               };
+                               map6 {
+                                    trip = <&cpu_alert4>;
+                                    cooling-device = <&cpu4 3 11>;
+                               };
                        };
                };
        };

diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 9b46b9fbac4e774b1542cde204f949bcc791b730..bf3c6f1ec4ee3c48b9a01a2b31ce97a87d67a00b 100644 (file)
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -32,6 +32,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu1: cpu@101 {
@@ -41,6 +44,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu2: cpu@102 {
@@ -50,6 +56,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu3: cpu@103 {
@@ -59,6 +68,9 @@
                        clock-frequency = <1000000000>;
                        cci-control-port = <&cci_control0>;
                        operating-points-v2 = <&cluster_a7_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <11>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu4: cpu@0 {
@@ -69,6 +81,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu5: cpu@1 {
@@ -78,6 +93,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu6: cpu@2 {
@@ -87,6 +105,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
 
                cpu7: cpu@3 {
@@ -96,6 +117,9 @@
                        clock-frequency = <1800000000>;
                        cci-control-port = <&cci_control1>;
                        operating-points-v2 = <&cluster_a15_opp_table>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <15>;
+                       #cooling-cells = <2>; /* min followed by max */
                };
        };
 };