ENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection

3 pairs of clock enable bits are required for CAAM clocking:
(1) wrapper IPG clock
(2) wrapper ACLK
(3) secure memory clock

IPG enable happened to be using an incorrect shift selection, which
had the net effect of leaving secure memory unclocked. Added the correct
shift selection in so that all 3 clock enable pairs are turned on.

Signed-off-by: Steve Cornelius <steve.cornelius@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 67c3d1fa6fd1010fe7de93ee9de533ef3e5171cf..bbddb94cd77413d58c847ac43c7c82d041d218b6 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -4244,7 +4244,7 @@ static struct clk caam_clk[] = {
         __INIT_CLK_DEBUG(caam_ipg_clk)
        .id = 2,
        .enable_reg = MXC_CCM_CCGR0,
-       .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
+       .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
        .enable = _clk_enable,
        .disable = _clk_disable,
        .parent = &mmdc_ch0_axi_clk[0],