/* Macros to access registers */
-/* Reset ADC FIFO */
-#define RtdAdcClearFifo(dev) \
- writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
-
/* Set ADC start conversion source select (write only) */
#define RtdAdcConversionSource(dev, v) \
writel(v, devpriv->las0+LAS0_ADC_CONVERSION)
static const unsigned limit = 0x2000;
unsigned fifo_size = 0;
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
rtd_load_channelgain_list(dev, 1, &chanspec);
RtdAdcConversionSource(dev, 0); /* software */
/* convert samples */
DRV_NAME);
return -EIO;
}
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
if (fifo_size != 0x400 && fifo_size != 0x2000) {
printk
(KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
int stat;
/* clear any old fifo data */
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
/* write channel to multiplexer and clear channel gain table */
rtd_load_channelgain_list(dev, 1, &insn->chanspec);
return IRQ_HANDLED;
abortTransfer:
- RtdAdcClearFifo(dev); /* clears full flag */
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
s->async->events |= COMEDI_CB_ERROR;
devpriv->aiCount = 0; /* stop and don't transfer any more */
/* fall into transferDone */
}
RtdDma0Reset(dev); /* reset onboard state */
#endif /* USE_DMA */
- RtdAdcClearFifo(dev); /* clear any old data */
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
RtdInterruptOverrunClear(dev);
devpriv->intCount = 0;
RtdInterruptClear(dev); /* clears bits set by mask */
RtdInterruptOverrunClear(dev);
writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
- RtdAdcClearFifo(dev);
+ writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
RtdDacClearFifo(dev, 0);
RtdDacClearFifo(dev, 1);
/* clear digital IO fifo */