powerpc/mm: Clear top 16 bits of va only on older cpus

As per ISA, we need to do this only for architecture version 2.02 and
earlier. This continued to work even for 2.07. But let's not do this for
anything after 2.02. ISA 3.0 requires these top bits to be not cleared.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index e53ebebff4744b7b3181d070e0a7c1d2cb6ce221..54471228f7b8f5c3517b59ab9e7e46a54644442d 100644 (file)
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -24,6 +24,11 @@
 /*
  * This is individual features
  */
+/*
+ * We need to clear top 16bits of va (from the remaining 64 bits )in
+ * tlbie* instructions
+ */
+#define MMU_FTR_TLBIE_CROP_VA          ASM_CONST(0x00008000)
 
 /* Enable use of high BAT registers */
 #define MMU_FTR_USE_HIGH_BATS          ASM_CONST(0x00010000)
@@ -97,7 +102,7 @@
 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2  \
        MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
 #define MMU_FTRS_POWER4                MMU_FTRS_DEFAULT_HPTE_ARCH_V2
-#define MMU_FTRS_PPC970                MMU_FTRS_POWER4
+#define MMU_FTRS_PPC970                MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
 #define MMU_FTRS_POWER5                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
 #define MMU_FTRS_POWER6                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
 #define MMU_FTRS_POWER7                MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
@@ -124,7 +129,7 @@ enum {
                MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
                MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
                MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
-               MMU_FTR_1T_SEGMENT |
+               MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
 #ifdef CONFIG_PPC_RADIX_MMU
                MMU_FTR_RADIX |
 #endif

diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index eeeacf6235a36d50ab05d86f3cca18a936298df3..d81f826d102967a3db7ad3f3992ee00119233d55 100644 (file)
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -137,7 +137,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER4 (gp)",
                .cpu_features           = CPU_FTRS_POWER4,
                .cpu_user_features      = COMMON_USER_POWER4,
-               .mmu_features           = MMU_FTRS_POWER4,
+               .mmu_features           = MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,
@@ -152,7 +152,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                .cpu_name               = "POWER4+ (gq)",
                .cpu_features           = CPU_FTRS_POWER4,
                .cpu_user_features      = COMMON_USER_POWER4,
-               .mmu_features           = MMU_FTRS_POWER4,
+               .mmu_features           = MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,
                .icache_bsize           = 128,
                .dcache_bsize           = 128,
                .num_pmcs               = 8,

diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index b0e0fdbe0273e36890b937ccc4999cd3ca487d6b..70521ef171fc95453a834e8c918e5267ab73b594 100644 (file)
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -64,7 +64,8 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
         * Older versions of the architecture (2.02 and earler) require the
         * masking of the top 16 bits.
         */
-       va &= ~(0xffffULL << 48);
+       if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
+               va &= ~(0xffffULL << 48);
 
        switch (psize) {
        case MMU_PAGE_4K:
@@ -113,7 +114,8 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
         * Older versions of the architecture (2.02 and earler) require the
         * masking of the top 16 bits.
         */
-       va &= ~(0xffffULL << 48);
+       if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
+               va &= ~(0xffffULL << 48);
 
        switch (psize) {
        case MMU_PAGE_4K: