MIPS: Malta: mux & enable SERIRQ interrupt

This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ
pin of the PIIX4 and to enable that interrupt. The kernel depends upon
the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but
previously would not configure it, instead relying upon the bootloader
having done so. If that is not the case then the typical result is that
the system appears to hang once it reaches userland as no output is
displayed on the UART.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6182/

diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index e33227998713e644a53e21c2e11c3e5fa174c970..836e2ede24de11252a7a4cce4a4008ed7756fee1 100644 (file)
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -26,6 +26,10 @@
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE       (1 << 7)
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK          0xf
 #define   PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX           16
+/* SERIRQ Control */
+#define PIIX4_FUNC0_SERIRQC                    0x64
+#define   PIIX4_FUNC0_SERIRQC_EN                       (1 << 7)
+#define   PIIX4_FUNC0_SERIRQC_CONT                     (1 << 6)
 /* Top Of Memory */
 #define PIIX4_FUNC0_TOM                                0x69
 #define   PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK           0xf0
@@ -34,6 +38,9 @@
 #define   PIIX4_FUNC0_DLC_USBPR_EN                     (1 << 2)
 #define   PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN           (1 << 1)
 #define   PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN       (1 << 0)
+/* General Configuration */
+#define PIIX4_FUNC0_GENCFG                     0xb0
+#define   PIIX4_FUNC0_GENCFG_SERIRQ                    (1 << 16)
 
 /* IDE Timing */
 #define PIIX4_FUNC1_IDETIM_PRIMARY_LO          0x40

diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index df36e2327c54572cca76848547cbbbf030c554ac..7a0eda782e35cf8c51d894c1b832dd9692f41c15 100644 (file)
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -54,6 +54,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 static void malta_piix_func0_fixup(struct pci_dev *pdev)
 {
        unsigned char reg_val;
+       u32 reg_val32;
        /* PIIX PIRQC[A:D] irq mappings */
        static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
                0,  0,  0,  3,
@@ -83,6 +84,16 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
                pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
                                PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
        }
+
+       /* Mux SERIRQ to its pin */
+       pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
+       pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
+                              reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
+
+       /* Enable SERIRQ */
+       pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
+       reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
+       pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,