Merge branch 'intc-external-irq' into soc

diff --cc arch/arm/mach-shmobile/Kconfig
index 04897a7f861a7e1ed249c1907f160a95061f205e,75d413c004b6f35f3f330e3f07c9bf3538d2ead5..0e4a820bcbe8396d3d195787b5d5f66d6c7d7d58
--- 1/arch/arm/mach-shmobile/Kconfig
--- 2/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@@ -16,16 -16,8 +16,17 @@@ config ARCH_SH73A
        select CPU_V7
        select I2C
        select SH_CLK_CPG
+       select RENESAS_INTC_IRQPIN
  
 +config ARCH_R8A73A4
 +      bool "R-Mobile APE6 (R8A73A40)"
 +      select ARCH_WANT_OPTIONAL_GPIOLIB
 +      select ARM_GIC
 +      select CPU_V7
 +      select ARM_ARCH_TIMER
 +      select SH_CLK_CPG
 +      select RENESAS_IRQC
 +
  config ARCH_R8A7740
        bool "R-Mobile A1 (R8A77400)"
        select ARCH_WANT_OPTIONAL_GPIOLIB

diff --cc arch/arm/mach-shmobile/board-kzm9g.c
Simple merge

diff --cc drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index cde4387edce15318435e0d8670f5ca25f8800e5f,6f15c03077a0f286f8b674b9341412544b0c11dc..587f7772abf2aa46b8608115829aad85d9cb500a
--- 1/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
--- 2/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@@ -3849,116 -2733,60 +3849,116 @@@ static const struct pinmux_data_reg pin
        { },
  };
  
- /* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
- #define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
- #define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
+ /* External IRQ pins mapped at IRQPIN_BASE */
+ #define EXT_IRQ16L(n) irq_pin(n)
+ #define EXT_IRQ16H(n) irq_pin(n)
  
 -static struct pinmux_irq pinmux_irqs[] = {
 -      PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
 -      PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
 -      PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
 -};
 -
 -struct sh_pfc_soc_info sh73a0_pinmux_info = {
 +static const struct pinmux_irq pinmux_irqs[] = {
 +      PINMUX_IRQ(EXT_IRQ16H(19), 9),
 +      PINMUX_IRQ(EXT_IRQ16L(1), 10),
 +      PINMUX_IRQ(EXT_IRQ16L(0), 11),
 +      PINMUX_IRQ(EXT_IRQ16H(18), 13),
 +      PINMUX_IRQ(EXT_IRQ16H(20), 14),
 +      PINMUX_IRQ(EXT_IRQ16H(21), 15),
 +      PINMUX_IRQ(EXT_IRQ16H(31), 26),
 +      PINMUX_IRQ(EXT_IRQ16H(30), 27),
 +      PINMUX_IRQ(EXT_IRQ16H(29), 28),
 +      PINMUX_IRQ(EXT_IRQ16H(22), 40),
 +      PINMUX_IRQ(EXT_IRQ16H(23), 53),
 +      PINMUX_IRQ(EXT_IRQ16L(10), 54),
 +      PINMUX_IRQ(EXT_IRQ16L(9), 56),
 +      PINMUX_IRQ(EXT_IRQ16H(26), 115),
 +      PINMUX_IRQ(EXT_IRQ16H(27), 116),
 +      PINMUX_IRQ(EXT_IRQ16H(28), 117),
 +      PINMUX_IRQ(EXT_IRQ16H(24), 118),
 +      PINMUX_IRQ(EXT_IRQ16L(6), 147),
 +      PINMUX_IRQ(EXT_IRQ16L(2), 149),
 +      PINMUX_IRQ(EXT_IRQ16L(7), 150),
 +      PINMUX_IRQ(EXT_IRQ16L(12), 156),
 +      PINMUX_IRQ(EXT_IRQ16L(4), 159),
 +      PINMUX_IRQ(EXT_IRQ16H(25), 164),
 +      PINMUX_IRQ(EXT_IRQ16L(8), 223),
 +      PINMUX_IRQ(EXT_IRQ16L(3), 224),
 +      PINMUX_IRQ(EXT_IRQ16L(5), 227),
 +      PINMUX_IRQ(EXT_IRQ16H(17), 234),
 +      PINMUX_IRQ(EXT_IRQ16L(11), 238),
 +      PINMUX_IRQ(EXT_IRQ16L(13), 239),
 +      PINMUX_IRQ(EXT_IRQ16H(16), 249),
 +      PINMUX_IRQ(EXT_IRQ16L(14), 251),
 +      PINMUX_IRQ(EXT_IRQ16L(9), 308),
 +};
 +
 +#define PORTnCR_PULMD_OFF     (0 << 6)
 +#define PORTnCR_PULMD_DOWN    (2 << 6)
 +#define PORTnCR_PULMD_UP      (3 << 6)
 +#define PORTnCR_PULMD_MASK    (3 << 6)
 +
 +static const unsigned int sh73a0_portcr_offsets[] = {
 +      0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
 +      0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
 +};
 +
 +static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
 +{
 +      void __iomem *addr = pfc->window->virt
 +                         + sh73a0_portcr_offsets[pin >> 5] + pin;
 +      u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
 +
 +      switch (value) {
 +      case PORTnCR_PULMD_UP:
 +              return PIN_CONFIG_BIAS_PULL_UP;
 +      case PORTnCR_PULMD_DOWN:
 +              return PIN_CONFIG_BIAS_PULL_DOWN;
 +      case PORTnCR_PULMD_OFF:
 +      default:
 +              return PIN_CONFIG_BIAS_DISABLE;
 +      }
 +}
 +
 +static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
 +                                 unsigned int bias)
 +{
 +      void __iomem *addr = pfc->window->virt
 +                         + sh73a0_portcr_offsets[pin >> 5] + pin;
 +      u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
 +
 +      switch (bias) {
 +      case PIN_CONFIG_BIAS_PULL_UP:
 +              value |= PORTnCR_PULMD_UP;
 +              break;
 +      case PIN_CONFIG_BIAS_PULL_DOWN:
 +              value |= PORTnCR_PULMD_DOWN;
 +              break;
 +      }
 +
 +      iowrite8(value, addr);
 +}
 +
 +static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
 +      .get_bias = sh73a0_pinmux_get_bias,
 +      .set_bias = sh73a0_pinmux_set_bias,
 +};
 +
 +const struct sh_pfc_soc_info sh73a0_pinmux_info = {
        .name = "sh73a0_pfc",
 -      .reserved_id = PINMUX_RESERVED,
 -      .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
 +      .ops = &sh73a0_pinmux_ops,
 +
        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
 -      .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
 -      .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 -      .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  
 -      .first_gpio = GPIO_PORT0,
 -      .last_gpio = GPIO_FN_FSIAISLD_PU,
 +      .pins = pinmux_pins,
 +      .nr_pins = ARRAY_SIZE(pinmux_pins),
 +      .ranges = pinmux_ranges,
 +      .nr_ranges = ARRAY_SIZE(pinmux_ranges),
 +      .groups = pinmux_groups,
 +      .nr_groups = ARRAY_SIZE(pinmux_groups),
 +      .functions = pinmux_functions,
 +      .nr_functions = ARRAY_SIZE(pinmux_functions),
 +
 +      .func_gpios = pinmux_func_gpios,
 +      .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
  
 -      .gpios = pinmux_gpios,
        .cfg_regs = pinmux_config_regs,
        .data_regs = pinmux_data_regs,