powerpc: Don't disable MSR bits in do_load_up_transact_*() functions

Similar to the non TM load_up_*() functions, don't disable the MSR
bits on the way out.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 9ad236e5d2c9d072540f1167107076e883af9ac3..38eb79b8a034940b6cca0988b432d75cf2db7bd4 100644 (file)
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -73,10 +73,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
        MTFSF_L(fr0)
        REST_32FPVSRS(0, R4, R7)
 
-       /* FP/VSX off again */
-       MTMSRD(r6)
-       SYNC
-
        blr
 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 

diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index f5c80d567d8d188734b9f2230622f843b5ae57f3..1c5425966204fc9f669f5ab988bc775e98163487 100644 (file)
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -29,10 +29,6 @@ _GLOBAL(do_load_up_transact_altivec)
        addi    r10,r3,THREAD_TRANSACT_VRSTATE
        REST_32VRS(0,r4,r10)
 
-       /* Disable VEC again. */
-       MTMSRD(r6)
-       isync
-
        blr
 #endif