ARM: zynq: Map I/O memory on clkc init

The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 17b4a94916d6d87c9d1fb9f42da49522594b5e2d..d93746cf29751e9ada09eb02ff9a5797cd186e9f 100644 (file)
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
 Required properties:
  - #clock-cells : Must be 1
  - compatible : "xlnx,ps7-clkc"
+ - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
  - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
                      (usually 33 MHz oscillators are used for Zynq platforms)
  - clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs:
  47: dbg_apb
 
 Example:
-       clkc: clkc {
+       clkc: clkc@100 {
                #clock-cells = <1>;
                compatible = "xlnx,ps7-clkc";
                ps-clk-frequency = <33333333>;
+               reg = <0x100 0x100>;
                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 81e5677f25a22aa2c5607a85f82f885d2e6df31a..602e12eedb01511d1bc4e09575501d0f7f1c78ba 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -123,30 +123,28 @@
                } ;
 
                slcr: slcr@f8000000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
                        compatible = "xlnx,zynq-slcr", "syscon";
                        reg = <0xF8000000 0x1000>;
-
-                       clocks {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-
-                               clkc: clkc {
-                                       #clock-cells = <1>;
-                                       compatible = "xlnx,ps7-clkc";
-                                       ps-clk-frequency = <33333333>;
-                                       fclk-enable = <0>;
-                                       clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-                                                       "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-                                                       "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
-                                                       "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
-                                                       "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
-                                                       "dma", "usb0_aper", "usb1_aper", "gem0_aper",
-                                                       "gem1_aper", "sdio0_aper", "sdio1_aper",
-                                                       "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
-                                                       "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
-                                                       "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
-                                                       "dbg_trc", "dbg_apb";
-                               };
+                       ranges;
+                       clkc: clkc@100 {
+                               #clock-cells = <1>;
+                               compatible = "xlnx,ps7-clkc";
+                               ps-clk-frequency = <33333333>;
+                               fclk-enable = <0>;
+                               clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                               "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                               "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                               "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                               "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                               "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                               "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                               "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                               "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                               "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                               "dbg_trc", "dbg_apb";
+                               reg = <0x100 0x100>;
                        };
                };
 

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 38401cf78383069a8f4e5c1b0230623bc9d46201..93ea19b13e6ee355badba81b08d68abfc08be3db 100644 (file)
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -67,7 +67,7 @@ static void __init zynq_timer_init(void)
 {
        zynq_early_slcr_init();
 
-       zynq_clock_init(zynq_slcr_base);
+       zynq_clock_init();
        clocksource_of_init();
 }
 

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 09dd0173ea0ae616dc4395f2b76724740310522c..03052d67b197c82ae754b5775d29899afe82dde8 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -21,34 +21,35 @@
 #include <linux/clk/zynq.h>
 #include <linux/clk-provider.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 #include <linux/io.h>
 
-static void __iomem *zynq_slcr_base_priv;
-
-#define SLCR_ARMPLL_CTRL               (zynq_slcr_base_priv + 0x100)
-#define SLCR_DDRPLL_CTRL               (zynq_slcr_base_priv + 0x104)
-#define SLCR_IOPLL_CTRL                        (zynq_slcr_base_priv + 0x108)
-#define SLCR_PLL_STATUS                        (zynq_slcr_base_priv + 0x10c)
-#define SLCR_ARM_CLK_CTRL              (zynq_slcr_base_priv + 0x120)
-#define SLCR_DDR_CLK_CTRL              (zynq_slcr_base_priv + 0x124)
-#define SLCR_DCI_CLK_CTRL              (zynq_slcr_base_priv + 0x128)
-#define SLCR_APER_CLK_CTRL             (zynq_slcr_base_priv + 0x12c)
-#define SLCR_GEM0_CLK_CTRL             (zynq_slcr_base_priv + 0x140)
-#define SLCR_GEM1_CLK_CTRL             (zynq_slcr_base_priv + 0x144)
-#define SLCR_SMC_CLK_CTRL              (zynq_slcr_base_priv + 0x148)
-#define SLCR_LQSPI_CLK_CTRL            (zynq_slcr_base_priv + 0x14c)
-#define SLCR_SDIO_CLK_CTRL             (zynq_slcr_base_priv + 0x150)
-#define SLCR_UART_CLK_CTRL             (zynq_slcr_base_priv + 0x154)
-#define SLCR_SPI_CLK_CTRL              (zynq_slcr_base_priv + 0x158)
-#define SLCR_CAN_CLK_CTRL              (zynq_slcr_base_priv + 0x15c)
-#define SLCR_CAN_MIOCLK_CTRL           (zynq_slcr_base_priv + 0x160)
-#define SLCR_DBG_CLK_CTRL              (zynq_slcr_base_priv + 0x164)
-#define SLCR_PCAP_CLK_CTRL             (zynq_slcr_base_priv + 0x168)
-#define SLCR_FPGA0_CLK_CTRL            (zynq_slcr_base_priv + 0x170)
-#define SLCR_621_TRUE                  (zynq_slcr_base_priv + 0x1c4)
-#define SLCR_SWDT_CLK_SEL              (zynq_slcr_base_priv + 0x304)
+static void __iomem *zynq_clkc_base;
+
+#define SLCR_ARMPLL_CTRL               (zynq_clkc_base + 0x00)
+#define SLCR_DDRPLL_CTRL               (zynq_clkc_base + 0x04)
+#define SLCR_IOPLL_CTRL                        (zynq_clkc_base + 0x08)
+#define SLCR_PLL_STATUS                        (zynq_clkc_base + 0x0c)
+#define SLCR_ARM_CLK_CTRL              (zynq_clkc_base + 0x20)
+#define SLCR_DDR_CLK_CTRL              (zynq_clkc_base + 0x24)
+#define SLCR_DCI_CLK_CTRL              (zynq_clkc_base + 0x28)
+#define SLCR_APER_CLK_CTRL             (zynq_clkc_base + 0x2c)
+#define SLCR_GEM0_CLK_CTRL             (zynq_clkc_base + 0x40)
+#define SLCR_GEM1_CLK_CTRL             (zynq_clkc_base + 0x44)
+#define SLCR_SMC_CLK_CTRL              (zynq_clkc_base + 0x48)
+#define SLCR_LQSPI_CLK_CTRL            (zynq_clkc_base + 0x4c)
+#define SLCR_SDIO_CLK_CTRL             (zynq_clkc_base + 0x50)
+#define SLCR_UART_CLK_CTRL             (zynq_clkc_base + 0x54)
+#define SLCR_SPI_CLK_CTRL              (zynq_clkc_base + 0x58)
+#define SLCR_CAN_CLK_CTRL              (zynq_clkc_base + 0x5c)
+#define SLCR_CAN_MIOCLK_CTRL           (zynq_clkc_base + 0x60)
+#define SLCR_DBG_CLK_CTRL              (zynq_clkc_base + 0x64)
+#define SLCR_PCAP_CLK_CTRL             (zynq_clkc_base + 0x68)
+#define SLCR_FPGA0_CLK_CTRL            (zynq_clkc_base + 0x70)
+#define SLCR_621_TRUE                  (zynq_clkc_base + 0xc4)
+#define SLCR_SWDT_CLK_SEL              (zynq_clkc_base + 0x204)
 
 #define NUM_MIO_PINS   54
 
@@ -569,8 +570,44 @@ static void __init zynq_clk_setup(struct device_node *np)
 
 CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
 
-void __init zynq_clock_init(void __iomem *slcr_base)
+void __init zynq_clock_init(void)
 {
-       zynq_slcr_base_priv = slcr_base;
+       struct device_node *np;
+       struct device_node *slcr;
+       struct resource res;
+
+       np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
+       if (!np) {
+               pr_err("%s: clkc node not found\n", __func__);
+               goto np_err;
+       }
+
+       if (of_address_to_resource(np, 0, &res)) {
+               pr_err("%s: failed to get resource\n", np->name);
+               goto np_err;
+       }
+
+       slcr = of_get_parent(np);
+
+       if (slcr->data) {
+               zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
+       } else {
+               pr_err("%s: Unable to get I/O memory\n", np->name);
+               of_node_put(slcr);
+               goto np_err;
+       }
+
+       pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
+
+       of_node_put(slcr);
+       of_node_put(np);
+
        of_clk_init(NULL);
+
+       return;
+
+np_err:
+       of_node_put(np);
+       BUG();
+       return;
 }

diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h
index e062d317cccea96d5e6f6c236fc2cec8ef3108a1..7a5633b71533932c54bc69a22d33d503b8d6e772 100644 (file)
--- a/include/linux/clk/zynq.h
+++ b/include/linux/clk/zynq.h
@@ -22,7 +22,7 @@
 
 #include <linux/spinlock.h>
 
-void zynq_clock_init(void __iomem *slcr);
+void zynq_clock_init(void);
 
 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,