ARM: dts: r8a73a4: Fix W=1 dtc warnings

Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property

Move the cache-controller nodes under the cpus node, and make their
unit names and reg properties match the MPIDR values.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 6954912a375379392f677c0595f4f96c99523dcc..ca8672778fe067e149d0e9e96af45759b60366fa 100644 (file)
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -31,6 +31,24 @@
                        power-domains = <&pd_a2sl>;
                        next-level-cache = <&L2_CA15>;
                };
+
+               L2_CA15: cache-controller@0 {
+                       compatible = "cache";
+                       reg = <0>;
+                       clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+                       power-domains = <&pd_a3sm>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+
+               L2_CA7: cache-controller@100 {
+                       compatible = "cache";
+                       reg = <0x100>;
+                       clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+                       power-domains = <&pd_a3km>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
        };
 
        ptm {
@@ -46,22 +64,6 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
-       L2_CA15: cache-controller@0 {
-               compatible = "cache";
-               clocks = <&cpg_clocks R8A73A4_CLK_Z>;
-               power-domains = <&pd_a3sm>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
-       L2_CA7: cache-controller@1 {
-               compatible = "cache";
-               clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
-               power-domains = <&pd_a3km>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
        dbsc1: memory-controller@e6790000 {
                compatible = "renesas,dbsc-r8a73a4";
                reg = <0 0xe6790000 0 0x10000>;