arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block

Remove register information used to reset and enable/disable clock
for AHB block as reseting AHB or disabling its clock will make other
peripherals attached to it stop working.

Signed-off-by: Duc Dang <dhdang@apm.com>

diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 718ffc431b19a467d90728df1ae904a834bf44fa..ddf1e86fa67ef981c988dfb9a2e07156c163de39 100644 (file)
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -140,17 +140,12 @@
                                clock-output-names = "socplldiv2";
                        };
 
-                       ahbclk: ahbclk@1f2ac000 {
+                       ahbclk: ahbclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
                                clocks = <&socplldiv2 0>;
-                               reg = <0x0 0x1f2ac000 0x0 0x1000
-                                       0x0 0x17000000 0x0 0x2000>;
-                               reg-names = "csr-reg", "div-reg";
-                               csr-offset = <0x0>;
-                               csr-mask = <0x1>;
-                               enable-offset = <0x8>;
-                               enable-mask = <0x1>;
+                               reg = <0x0 0x17000000 0x0 0x2000>;
+                               reg-names = "div-reg";
                                divider-offset = <0x164>;
                                divider-width = <0x5>;
                                divider-shift = <0x0>;

diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index 445f68d830512a4f3ecf43cc76824025de48468c..32f9ba9b696244f01ccba1d3c6eb8891f4161e47 100644 (file)
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -150,17 +150,12 @@
                                clock-output-names = "socplldiv2";
                        };
 
-                       ahbclk: ahbclk@1f2ac000 {
+                       ahbclk: ahbclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
                                clocks = <&socplldiv2 0>;
-                               reg = <0x0 0x1f2ac000 0x0 0x1000
-                                       0x0 0x17000000 0x0 0x2000>;
-                               reg-names = "csr-reg", "div-reg";
-                               csr-offset = <0x0>;
-                               csr-mask = <0x1>;
-                               enable-offset = <0x8>;
-                               enable-mask = <0x1>;
+                               reg = <0x0 0x17000000 0x0 0x2000>;
+                               reg-names = "div-reg";
                                divider-offset = <0x164>;
                                divider-width = <0x5>;
                                divider-shift = <0x0>;