ath9k: Fix antenna control init for AR9485

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 178052fc4d8842163f16ad4ff0f014912eb923c3..abdc7ee874139b26e42ded779d42da8295d05775 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3614,6 +3614,11 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
        }
 
        value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
+       if (AR_SREV_9485(ah) && common->bt_ant_diversity) {
+               regval &= ~AR_SWITCH_TABLE_COM2_ALL;
+               regval |= ah->config.ant_ctrl_comm2g_switch_enable;
+
+       }
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
 
        if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) {
@@ -3645,6 +3650,9 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
                regval &= (~AR_PHY_ANT_DIV_LNADIV);
                regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
 
+               if (AR_SREV_9485(ah) && common->bt_ant_diversity)
+                       regval |= AR_ANT_DIV_ENABLE;
+
                if (AR_SREV_9565(ah)) {
                        if (common->bt_ant_diversity) {
                                regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);
@@ -3656,10 +3664,14 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
 
                REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 
-               /*enable fast_div */
+               /* enable fast_div */
                regval = REG_READ(ah, AR_PHY_CCK_DETECT);
                regval &= (~AR_FAST_DIV_ENABLE);
                regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
+
+               if (AR_SREV_9485(ah) && common->bt_ant_diversity)
+                       regval |= AR_FAST_DIV_ENABLE;
+
                REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
 
                if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {