u32 intstat;
};
-static DEFINE_SPINLOCK(gpio_lock);
-
#define chip2controller(chip) \
container_of(chip, struct davinci_gpio_controller, chip)
{
struct davinci_gpio_controller *d = chip2controller(chip);
struct davinci_gpio_regs __iomem *g = d->regs;
+ unsigned long flags;
u32 temp;
u32 mask = 1 << offset;
- spin_lock(&gpio_lock);
+ spin_lock_irqsave(&d->lock, flags);
temp = __raw_readl(&g->dir);
if (out) {
temp &= ~mask;
temp |= mask;
}
__raw_writel(temp, &g->dir);
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&d->lock, flags);
return 0;
}
if (chips[i].chip.ngpio > 32)
chips[i].chip.ngpio = 32;
+ spin_lock_init(&chips[i].lock);
+
regs = gpio2regs(base);
chips[i].regs = regs;
chips[i].set_data = ®s->set_data;