ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <750000000>;
+ };
+
core_intc: arc700-intc@cpu {
compatible = "snps,arc700-intc";
interrupt-controller;
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <90000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <90000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
bus addr, parent bus addr, size */
ranges = <0x80000000 0x0 0x80000000 0x80000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <80000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
core_intc: interrupt-controller {
compatible = "snps,arc700-intc";
interrupt-controller;
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
/* child and parent address space 1:1 mapped */
ranges;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <5000000>;
+ };
+
core_intc: core-interrupt-controller {
compatible = "snps,archs-intc";
interrupt-controller;
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
ranges = <0x00000000 0xf0000000 0x10000000>;
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
core_intc: archs-intc@cpu {
compatible = "snps,archs-intc";
interrupt-controller;
*
*/
+#include <linux/of_fdt.h>
#include <linux/of_platform.h>
+#include <linux/libfdt.h>
#include <asm/asm-offsets.h>
#include <asm/clk.h>
static void __init axs103_early_init(void)
{
- u32 freq = arc_get_core_freq(), orig = freq;
+ int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
+ const struct fdt_property *prop = fdt_get_property(initial_boot_params,
+ offset,
+ "clock-frequency",
+ NULL);
+ u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq;
/*
* AXS103 configurations for SMP/QUAD configurations share device tree
}
pr_info("Freq is %dMHz\n", freq);
+
+ /* Patching .dtb in-place with new core clock value */
if (freq != orig ) {
arc_set_core_freq(freq * 1000000);
+ freq = cpu_to_be32(freq * 1000000);
+ fdt_setprop_inplace(initial_boot_params, offset,
+ "clock-frequency", &freq, sizeof(freq));
}
/* Memory maps already config in pre-bootloader */