}
#endif
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cscmr1);
+ reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+ MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, &imx_ccm->cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+ * disable the clock gate
+ * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+ * disable both of them.
+ */
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, &imx_ccm->cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */
#define AIPS3_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
-#define QSPI1_ARB_BASE_ADDR 0x60000000
-#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
-#define QSPI2_ARB_BASE_ADDR 0x70000000
-#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
+#define QSPI0_AMBA_BASE 0x60000000
+#define QSPI0_AMBA_END 0x6FFFFFFF
+#define QSPI1_AMBA_BASE 0x70000000
+#define QSPI1_AMBA_END 0x7FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
F: board/freescale/mx6slevk/
F: include/configs/mx6slevk.h
F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spinor_defconfig
return 0;
}
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+ MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA07__QSPI2_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+ MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+ /* Set the iomux */
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ ARRAY_SIZE(quadspi_pads));
+
+ /* Set the clock */
+ enable_qspi_clk(1);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* Address of boot parameters */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
+#ifdef CONFIG_FSL_QSPI
+ board_qspi_init();
+#endif
+
return 0;
}
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SLEVK=y
#endif
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
-obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs
- * with an interface identical to SPI flash devices.
- * However since they behave like RAM there are no delays or
- * busy polls required. They can sustain read or write at the
- * allowed SPI bus speed, which can be 40 MHz for some devices.
- *
- * Unfortunately some RAMTRON devices do not have a means of
- * identifying them. They will leave the SO line undriven when
- * the READ-ID command is issued. It is therefore mandatory
- * that the MISO line has a proper pull-up, so that READ-ID
- * will return a row of 0xff. This 0xff pseudo-id will cause
- * probes by all vendor specific functions that are designed
- * to handle it. If the MISO line is not pulled up, READ-ID
- * could return any random noise, even mimicking another
- * device.
- *
- * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- * to define which device will be assumed after a simple status
- * register verify. This method is prone to false positive
- * detection and should therefore be the last to be tried.
- * Enter it in the last position in the table in spi_flash.c!
- *
- * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates
- * compilation of the special handler and defines the device
- * to assume.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-#include <spi_flash.h>
-#include "sf_internal.h"
-
-/*
- * Properties of supported FRAMs
- * Note: speed is currently not used because we have no method to deliver that
- * value to the upper layers
- */
-struct ramtron_spi_fram_params {
- u32 size; /* size in bytes */
- u8 addr_len; /* number of address bytes */
- u8 merge_cmd; /* some address bits are in the command byte */
- u8 id1; /* device ID 1 (family, density) */
- u8 id2; /* device ID 2 (sub, rev, rsvd) */
- u32 speed; /* max. SPI clock in Hz */
- const char *name; /* name for display and/or matching */
-};
-
-struct ramtron_spi_fram {
- struct spi_flash flash;
- const struct ramtron_spi_fram_params *params;
-};
-
-static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
- *flash)
-{
- return container_of(flash, struct ramtron_spi_fram, flash);
-}
-
-/*
- * table describing supported FRAM chips:
- * chips without RDID command must have the values 0xff for id1 and id2
- */
-static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = {
- {
- .size = 32*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x22,
- .id2 = 0x00,
- .speed = 40000000,
- .name = "FM25V02",
- },
- {
- .size = 32*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x22,
- .id2 = 0x01,
- .speed = 40000000,
- .name = "FM25VN02",
- },
- {
- .size = 64*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x23,
- .id2 = 0x00,
- .speed = 40000000,
- .name = "FM25V05",
- },
- {
- .size = 64*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x23,
- .id2 = 0x01,
- .speed = 40000000,
- .name = "FM25VN05",
- },
- {
- .size = 128*1024,
- .addr_len = 3,
- .merge_cmd = 0,
- .id1 = 0x24,
- .id2 = 0x00,
- .speed = 40000000,
- .name = "FM25V10",
- },
- {
- .size = 128*1024,
- .addr_len = 3,
- .merge_cmd = 0,
- .id1 = 0x24,
- .id2 = 0x01,
- .speed = 40000000,
- .name = "FM25VN10",
- },
-#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- {
- .size = 256*1024,
- .addr_len = 3,
- .merge_cmd = 0,
- .id1 = 0xff,
- .id2 = 0xff,
- .speed = 40000000,
- .name = "FM25H20",
- },
-#endif
-};
-
-static int ramtron_common(struct spi_flash *flash,
- u32 offset, size_t len, void *buf, u8 command)
-{
- struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash);
- u8 cmd[4];
- int cmd_len;
- int ret;
-
- if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) {
- cmd[0] = command;
- cmd[1] = offset >> 16;
- cmd[2] = offset >> 8;
- cmd[3] = offset;
- cmd_len = 4;
- } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) {
- cmd[0] = command;
- cmd[1] = offset >> 8;
- cmd[2] = offset;
- cmd_len = 3;
- } else {
- printf("SF: unsupported addr_len or merge_cmd\n");
- return -1;
- }
-
- /* claim the bus */
- ret = spi_claim_bus(flash->spi);
- if (ret) {
- debug("SF: Unable to claim SPI bus\n");
- return ret;
- }
-
- if (command == CMD_PAGE_PROGRAM) {
- /* send WREN */
- ret = spi_flash_cmd_write_enable(flash);
- if (ret < 0) {
- debug("SF: Enabling Write failed\n");
- goto releasebus;
- }
- }
-
- /* do the transaction */
- if (command == CMD_PAGE_PROGRAM)
- ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len);
- else
- ret = spi_flash_cmd_read(flash->spi, cmd, cmd_len, buf, len);
- if (ret < 0)
- debug("SF: Transaction failed\n");
-
-releasebus:
- /* release the bus */
- spi_release_bus(flash->spi);
- return ret;
-}
-
-static int ramtron_read(struct spi_flash *flash,
- u32 offset, size_t len, void *buf)
-{
- return ramtron_common(flash, offset, len, buf,
- CMD_READ_ARRAY_SLOW);
-}
-
-static int ramtron_write(struct spi_flash *flash,
- u32 offset, size_t len, const void *buf)
-{
- return ramtron_common(flash, offset, len, (void *)buf,
- CMD_PAGE_PROGRAM);
-}
-
-static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
-{
- debug("SF: Erase of RAMTRON FRAMs is pointless\n");
- return -1;
-}
-
-/*
- * nore: we are called here with idcode pointing to the first non-0x7f byte
- * already!
- */
-static struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi,
- u8 *idcode)
-{
- const struct ramtron_spi_fram_params *params;
- struct ramtron_spi_fram *sn;
- unsigned int i;
-#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- int ret;
- u8 sr;
-#endif
-
- /* NOTE: the bus has been claimed before this function is called! */
- switch (idcode[0]) {
- case 0xc2:
- /* JEDEC conformant RAMTRON id */
- for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
- params = &ramtron_spi_fram_table[i];
- if (idcode[1] == params->id1 &&
- idcode[2] == params->id2)
- goto found;
- }
- break;
-#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- case 0xff:
- /*
- * probably open MISO line, pulled up.
- * We COULD have a non JEDEC conformant FRAM here,
- * read the status register to verify
- */
- ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1);
- if (ret)
- return NULL;
-
- /* Bits 5,4,0 are fixed 0 for all devices */
- if ((sr & 0x31) != 0x00)
- return NULL;
- /* now find the device */
- for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) {
- params = &ramtron_spi_fram_table[i];
- if (!strcmp(params->name,
- CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC))
- goto found;
- }
- debug("SF: Unsupported non-JEDEC RAMTRON device "
- CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC "\n");
- break;
-#endif
- default:
- break;
- }
-
- /* arriving here means no method has found a device we can handle */
- debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n",
- idcode[0], idcode[1], idcode[2]);
- return NULL;
-
-found:
- sn = malloc(sizeof(*sn));
- if (!sn) {
- debug("SF: Failed to allocate memory\n");
- return NULL;
- }
-
- sn->params = params;
-
- sn->flash.write = ramtron_write;
- sn->flash.read = ramtron_read;
- sn->flash.erase = ramtron_erase;
- sn->flash.size = params->size;
-
- return &sn->flash;
-}
-
-/*
- * The following table holds all device probe functions
- * (All flashes are removed and implemented a common probe at
- * spi_flash_probe.c)
- *
- * shift: number of continuation bytes before the ID
- * idcode: the expected IDCODE or 0xff for non JEDEC devices
- * probe: the function to call
- *
- * Non JEDEC devices should be ordered in the table such that
- * the probe functions with best detection algorithms come first.
- *
- * Several matching entries are permitted, they will be tried
- * in sequence until a probe function returns non NULL.
- *
- * IDCODE_CONT_LEN may be redefined if a device needs to declare a
- * larger "shift" value. IDCODE_PART_LEN generally shouldn't be
- * changed. This is the max number of bytes probe functions may
- * examine when looking up part-specific identification info.
- *
- * Probe functions will be given the idcode buffer starting at their
- * manu id byte (the "idcode" in the table below). In other words,
- * all of the continuation bytes will be skipped (the "shift" below).
- */
-#define IDCODE_CONT_LEN 0
-#define IDCODE_PART_LEN 5
-static const struct {
- const u8 shift;
- const u8 idcode;
- struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
-} flashes[] = {
- /* Keep it sorted by define name */
-#ifdef CONFIG_SPI_FRAM_RAMTRON
- { 6, 0xc2, spi_fram_probe_ramtron, },
-# undef IDCODE_CONT_LEN
-# define IDCODE_CONT_LEN 6
-#endif
-#ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- { 0, 0xff, spi_fram_probe_ramtron, },
-#endif
-};
-#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
-
-struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int spi_mode)
-{
- struct spi_slave *spi;
- struct spi_flash *flash = NULL;
- int ret, i, shift;
- u8 idcode[IDCODE_LEN], *idp;
-
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
- if (!spi) {
- printf("SF: Failed to set up slave\n");
- return NULL;
- }
-
- ret = spi_claim_bus(spi);
- if (ret) {
- debug("SF: Failed to claim SPI bus: %d\n", ret);
- goto err_claim_bus;
- }
-
- /* Read the ID codes */
- ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
- if (ret)
- goto err_read_id;
-
-#ifdef DEBUG
- printf("SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
-
- /* count the number of continuation bytes */
- for (shift = 0, idp = idcode;
- shift < IDCODE_CONT_LEN && *idp == 0x7f;
- ++shift, ++idp)
- continue;
-
- /* search the table for matches in shift and id */
- for (i = 0; i < ARRAY_SIZE(flashes); ++i)
- if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
- /* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
- break;
- }
-
- if (!flash) {
- printf("SF: Unsupported manufacturer %02x\n", *idp);
- goto err_manufacturer_probe;
- }
-
- printf("SF: Detected %s with total size ", flash->name);
- print_size(flash->size, "");
- puts("\n");
-
- spi_release_bus(spi);
-
- return flash;
-
-err_manufacturer_probe:
-err_read_id:
- spi_release_bus(spi);
-err_claim_bus:
- spi_free_slave(spi);
- return NULL;
-}
-
-void spi_flash_free(struct spi_flash *flash)
-{
- spi_free_slave(flash->spi);
- free(flash);
-}
{"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
{"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
{"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"S25FL116K", 0x014015, 0x0, 64 * 1024, 128, RD_NORM, 0},
+ {"S25FL164K", 0x014017, 0x0140, 64 * 1024, 128, RD_NORM, 0},
{"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
{"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
+ {"SST25WF040B", 0x621613, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
#include "fsl_qspi.h"
#define RX_BUFFER_SIZE 0x80
+#ifdef CONFIG_MX6SX
+#define TX_BUFFER_SIZE 0x200
+#else
#define TX_BUFFER_SIZE 0x40
+#endif
#define OFFSET_BITS_MASK 0x00ffffff
#define SEQID_CHIP_ERASE 5
#define SEQID_PP 6
#define SEQID_RDID 7
-
-/* Flash opcodes */
-#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
-#define OPCODE_RDSR 0x05 /* Read status register */
-#define OPCODE_WREN 0x06 /* Write enable */
-#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
-#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
-#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
-#define OPCODE_RDID 0x9f /* Read JEDEC ID */
-
-/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
-#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
-#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
-#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+#define SEQID_BE_4K 8
+
+/* QSPI CMD */
+#define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */
+#define QSPI_CMD_RDSR 0x05 /* Read status register */
+#define QSPI_CMD_WREN 0x06 /* Write enable */
+#define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */
+#define QSPI_CMD_BE_4K 0x20 /* 4K erase */
+#define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+#define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */
+#define QSPI_CMD_RDID 0x9f /* Read JEDEC ID */
+
+/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
+#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
+#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
+#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
#ifdef CONFIG_SYS_FSL_QSPI_LE
#define qspi_read32 in_le32
static unsigned long spi_bases[] = {
QSPI0_BASE_ADDR,
+#ifdef CONFIG_MX6SX
+ QSPI1_BASE_ADDR,
+#endif
};
static unsigned long amba_bases[] = {
QSPI0_AMBA_BASE,
+#ifdef CONFIG_MX6SX
+ QSPI1_AMBA_BASE,
+#endif
};
struct fsl_qspi {
/* Write Enable */
lut_base = SEQID_WREN * 4;
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_WREN) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(®s->lut[lut_base + 1], 0);
qspi_write32(®s->lut[lut_base + 2], 0);
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
- PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
- PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+ qspi_write32(®s->lut[lut_base],
+ OPRND0(QSPI_CMD_FAST_READ_4B) |
+ PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
+ OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
+ INSTR1(LUT_ADDR));
qspi_write32(®s->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
/* Read Status */
lut_base = SEQID_RDSR * 4;
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDSR) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(®s->lut[lut_base + 1], 0);
/* Erase a sector */
lut_base = SEQID_SE * 4;
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_SE_4B) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(®s->lut[lut_base + 1], 0);
/* Erase the whole chip */
lut_base = SEQID_CHIP_ERASE * 4;
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_CHIP_ERASE) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(®s->lut[lut_base + 1], 0);
qspi_write32(®s->lut[lut_base + 2], 0);
/* Page Program */
lut_base = SEQID_PP * 4;
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+#ifdef CONFIG_MX6SX
+ /*
+ * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
+ * So, Use IDATSZ in IPCR to determine the size and here set 0.
+ */
+ qspi_write32(®s->lut[lut_base + 1], OPRND0(0) |
+ PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#else
qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#endif
qspi_write32(®s->lut[lut_base + 2], 0);
qspi_write32(®s->lut[lut_base + 3], 0);
/* READ ID */
lut_base = SEQID_RDID * 4;
- qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_RDID) |
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(®s->lut[lut_base + 1], 0);
qspi_write32(®s->lut[lut_base + 2], 0);
qspi_write32(®s->lut[lut_base + 3], 0);
+ /* SUB SECTOR 4K ERASE */
+ lut_base = SEQID_BE_4K * 4;
+ qspi_write32(®s->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
+ PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+ PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+
/* Lock the LUT */
qspi_write32(®s->lutkey, LUT_KEY_VALUE);
qspi_write32(®s->lckcr, QSPI_LCKCR_LOCK);
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
+ if (cs >= FSL_QSPI_FLASH_NUM)
+ return NULL;
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
if (!qspi)
return NULL;
qspi->reg_base = spi_bases[bus];
- qspi->amba_base = amba_bases[bus];
+ /*
+ * According cs, use different amba_base to choose the
+ * corresponding flash devices.
+ *
+ * If not, only one flash device is used even if passing
+ * different cs using `sf probe`
+ */
+ qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
qspi->slave.max_write_size = TX_BUFFER_SIZE;
qspi_write32(®s->mcr, QSPI_MCR_RESERVED_MASK);
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
- qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
- qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | qspi->amba_base);
- qspi_write32(®s->sfb1ad, total_size | qspi->amba_base);
- qspi_write32(®s->sfb2ad, total_size | qspi->amba_base);
+ /*
+ * Any read access to non-implemented addresses will provide
+ * undefined results.
+ *
+ * In case single die flash devices, TOP_ADDR_MEMA2 and
+ * TOP_ADDR_MEMB2 should be initialized/programmed to
+ * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
+ * setting the size of these devices to 0. This would ensure
+ * that the complete memory map is assigned to only one flash device.
+ */
+ qspi_write32(®s->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+ qspi_write32(®s->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+ qspi_write32(®s->sfb1ad, total_size | amba_bases[bus]);
+ qspi_write32(®s->sfb2ad, total_size | amba_bases[bus]);
qspi_set_lut(qspi);
qspi_write32(®s->mcr, mcr_reg);
}
-static void qspi_op_se(struct fsl_qspi *qspi)
+static void qspi_op_erase(struct fsl_qspi *qspi)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
u32 mcr_reg;
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
;
- qspi_write32(®s->ipcr,
- (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
+ if (qspi->cur_seqid == QSPI_CMD_SE) {
+ qspi_write32(®s->ipcr,
+ (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
+ } else if (qspi->cur_seqid == QSPI_CMD_BE_4K) {
+ qspi_write32(®s->ipcr,
+ (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
+ }
while (qspi_read32(®s->sr) & QSPI_SR_BUSY_MASK)
;
return 0;
}
- if (qspi->cur_seqid == OPCODE_FAST_READ) {
+ if (qspi->cur_seqid == QSPI_CMD_FAST_READ) {
qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
- } else if (qspi->cur_seqid == OPCODE_SE) {
+ } else if ((qspi->cur_seqid == QSPI_CMD_SE) ||
+ (qspi->cur_seqid == QSPI_CMD_BE_4K)) {
qspi->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
- qspi_op_se(qspi);
- } else if (qspi->cur_seqid == OPCODE_PP) {
+ qspi_op_erase(qspi);
+ } else if (qspi->cur_seqid == QSPI_CMD_PP) {
pp_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
}
}
if (din) {
- if (qspi->cur_seqid == OPCODE_FAST_READ)
+ if (qspi->cur_seqid == QSPI_CMD_FAST_READ)
qspi_op_read(qspi, din, bytes);
- else if (qspi->cur_seqid == OPCODE_RDID)
+ else if (qspi->cur_seqid == QSPI_CMD_RDID)
qspi_op_rdid(qspi, din, bytes);
- else if (qspi->cur_seqid == OPCODE_RDSR)
+ else if (qspi->cur_seqid == QSPI_CMD_RDSR)
qspi_op_rdsr(qspi, din);
}
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
+
+#if defined CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#else
+#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_IS_IN_MMC
+#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define FSL_QSPI_FLASH_SIZE SZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
projects / karo-tx-uboot.git / commitdiff